On Thu, 28 Aug 2003, Marc Aurele La France wrote: > On 28 Aug 2003, John Dennis wrote: > > On Thu, 2003-08-28 at 12:46, Marc Aurele La France wrote: > > > Secondly, EFI is already doing the wrong thing by marking PCI ROMs as > > > non-cacheable. This doesn't inspire confidence...
> > I believe there is a difference between ROM's being logically cacheable > > and the way the ZX1 actually "wires" that memory into the memory system. > > The ZX1 connection to PCI devices are always non-cached. It's a > > simplified assumption correct in most all cases with little penalty for > > the rare case of cacheable memory sitting out in MMIO space. Therefore > > EFI is not doing the wrong thing by marking ROM as non-cacheable, the > > ZX1 is going to treat any PCI address as non-cached by design. > ... which basically means that framebuffers cannot benifit from CPU > caching. I don't beleive this to be the case. Further to this, it appears you don't realise that the frambuffers we're talking about here, _are_ in PCI space. Marc. +----------------------------------+-----------------------------------+ | Marc Aurele La France | work: 1-780-492-9310 | | Computing and Network Services | fax: 1-780-492-1729 | | 352 General Services Building | email: [EMAIL PROTECTED] | | University of Alberta +-----------------------------------+ | Edmonton, Alberta | | | T6G 2H1 | Standard disclaimers apply | | CANADA | | +----------------------------------+-----------------------------------+ XFree86 Core Team member. ATI driver and X server internals. _______________________________________________ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
