John Dennis writes: > > I will confess my understanding is weak when it comes to low level bus > interactions, but I'm learning more eveytime I have to tackle these > issues ;-) > > Correct me if I'm wrong, but I thought things like caching and > write-combining are not properties of the PCI device, rather they are > properties of the memory system upstream of the PCI device, e.g. > bridges, memory controllers, and the MMU in the CPU.
Right. > > The PCI configuration does provide various pieces of information which > help determine how the device can be accessed, e.g. pre-fetch, latency, > cache line size etc. All of this is available to firmware. Wouldn't all > this be sufficient for firmware to make the right decisions? > That's what I would like to know. I was hoping our contacts to HW vendors would provide us answers to these questions. Some of these questions seemed to have been answered in one of your previous posts - at least as far as HP's IA64 boxes are concerend. The chipset simply definces *all* IO (access to PCI buses) as uncached. So nobody bothers to derive such properties from information provided by the PCI devices. Egbert. _______________________________________________ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
