On Tue, 2003-08-26 at 13:40, Egbert Eich wrote: > Marc Aurele La France writes: > > On Tue, 26 Aug 2003, Egbert Eich wrote: > > > > > > Frankly, I don't see how this EFI MDT can be accurate given that, in > > general, whether or not a particular PCI memory assignment will tolerate > > caching and/or write-combining is highly device-specific. That would be a > > horrific PCI device database for EFI to maintain. > > > > How that is done is in fact an interesting question. Maybe someone > with good contacts to HP could inquire on this.
I will confess my understanding is weak when it comes to low level bus interactions, but I'm learning more eveytime I have to tackle these issues ;-) Correct me if I'm wrong, but I thought things like caching and write-combining are not properties of the PCI device, rather they are properties of the memory system upstream of the PCI device, e.g. bridges, memory controllers, and the MMU in the CPU. The PCI configuration does provide various pieces of information which help determine how the device can be accessed, e.g. pre-fetch, latency, cache line size etc. All of this is available to firmware. Wouldn't all this be sufficient for firmware to make the right decisions? _______________________________________________ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
