On 26 Aug 2003, John Dennis wrote: > The PCI configuration does provide various pieces of information which > help determine how the device can be accessed, e.g. pre-fetch, latency, > cache line size etc. All of this is available to firmware. Wouldn't all > this be sufficient for firmware to make the right decisions?
Yes and no. EFI also needs to always do the "right thing", which is to ensure all BAR and ROM pointer assignments are valid. For XFree86, this includes all graphics devices, not just the active ones. And the kernel likely has other ideas on this too. If re-assignments are ever needed (by the kernel or XFree86), mayhem is likely to occur. Secondly, EFI is already doing the wrong thing by marking PCI ROMs as non-cacheable. This doesn't inspire confidence... It occurs to me that we should probably change XAA to flush CPU caches just after calling the driver's Sync() function, and change mibank to do the same after telling the driver to switch banks. Marc. +----------------------------------+-----------------------------------+ | Marc Aurele La France | work: 1-780-492-9310 | | Computing and Network Services | fax: 1-780-492-1729 | | 352 General Services Building | email: [EMAIL PROTECTED] | | University of Alberta +-----------------------------------+ | Edmonton, Alberta | | | T6G 2H1 | Standard disclaimers apply | | CANADA | | +----------------------------------+-----------------------------------+ XFree86 Core Team member. ATI driver and X server internals. _______________________________________________ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
