On Wed, 16 Aug 2017 at 23:11:32 +0200 Adam Borowski <kilob...@angband.pl> wrote:
> On Wed, Aug 16, 2017 at 01:26:15PM -0700, Rick Moen wrote: > > I'm watching the J-Core project, which has resurrected the Hitachi > > SuperH SH3/SH4 architecture as the patents expire, and should have a > > fully fleshed 64-bit RISC system out in a couple of years. At that > > point, you'll have reasonably modern, general-purpose computing with no > > blackbox hardware/firmware/software subsystems whatsoever. > > http://j-core.org/ > > Alas, they seem to be suspiciously quiet within the last year or so. Plus, it seems to target SoC and IoT devices rather than desktops: http://j-core.org/roadmap.html "This is a NOMMU chip, implemented as Harvard architecture (separate Instruction and Data busses) with a 5 stage pipeline, with 16k cache (8k instruction, 8k data), supported by a memory controller interfacing with up to 256 megabytes of lpddr memory (in one low cost memory chip)." So, it's a 32-bit chip with no MMU, no FPU, 2-way SMP and 256 MiB maximum memory. :-( Alessandro _______________________________________________ Dng mailing list Dng@lists.dyne.org https://mailinglists.dyne.org/cgi-bin/mailman/listinfo/dng
