Quoting Alessandro Selli (alessandrose...@linux.com): > >> "This is a NOMMU chip, implemented as Harvard architecture (separate > >> Instruction and Data busses) with a 5 stage pipeline, with 16k cache (8k > >> instruction, 8k data), supported by a memory controller interfacing with > >> up to 256 megabytes of lpddr memory (in one low cost memory chip)." > >> > >> So, it's a 32-bit chip with no MMU, no FPU, 2-way SMP and 256 MiB > >> maximum memory. :-( > > > > When you say 'it', you refer to the SH2-compatible chip from 2015, which > > was merely the -start- of the Hitachi SuperH-revival project. > > No, 2-way SMP support was added in 2016. Looks like that was the last > release.
But the text you quoted (above) described the 2015 SH2-compatible chip, exactly as I said, not the 2016 one. Thus my point. You described only the _start_ of the roadmap. You said nothing (until now) about even the 2016 immediate successor. > > Why did you ignore the rest of the roadmap? > > Because it's just a roadmap. I wrote about what is available now. What is available now is not all that interesting. The great thing is that doing SH3 and SH4, the next steps, is _not_ from-scratch work, because the former Hitachi implementation is fully documented -- and now also patent-free. This is outside my field, so I don't really know the extent of the work needing doing, but I gather that leveraging Hitachi's prior art reduces the workload quite a lot. _______________________________________________ Dng mailing list Dng@lists.dyne.org https://mailinglists.dyne.org/cgi-bin/mailman/listinfo/dng
