On 6/24/24 11:06 AM, Alexander Stein wrote:
Am Montag, 24. Juni 2024, 09:45:13 CEST schrieb Alexander Stein:
Hi,
Am Sonntag, 23. Juni 2024, 16:38:36 CEST schrieb Marek Vasut:
The MIPI_DSI_CLOCK_NON_CONTINUOUS causes visible artifacts in high
resolution modes, disable it. Namely, in DSI->DP mode 1920x1200 24
bpp 59.95 Hz, with DSI bus at maximum 1 Gbps per lane setting, the
image contains jittering empty lines.
Signed-off-by: Marek Vasut <ma...@denx.de>
I can't see these artifacts in 1920x1200 24bpp, but still looks good to me
Acked-by: Alexander Stein <alexander.st...@ew.tq-group.com>
I have to retract that. After checking for those mentioned artifacts
I noticed that the DP output was running without any issues.
There is something more going on here. Reverting this patch there wasn't
a single output problem.
This changes actually breaks my DSI connection randomly.
Sometimes it works, sometimes not. I also noticed that there wasn't even
a single DP link training failure, so I assume the DSI clock somehow
affected the internal state machine which even affected DP link training.
Until we know what's going on, NAK form me.
I can temporarily drop this patch and keep the remaining five if that's
OK with you ?
