On 7/22/2025 8:00 PM, Konrad Dybcio wrote: > On 7/20/25 2:16 PM, Akhil P Oommen wrote: >> A minor refactor to combine the subroutines for legacy a6xx GMUs under >> a single check. This helps to avoid an unnecessary check and return >> early from the subroutine for majority of a6xx gpus. >> >> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> index >> 38c0f8ef85c3d260864541d83abe43e49c772c52..41129692d127b70e9293b82bea5ccb6b911b0bfb >> 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -403,7 +403,10 @@ int a6xx_sptprac_enable(struct a6xx_gmu *gmu) >> int ret; >> u32 val; >> >> - if (!gmu->legacy) >> + WARN_ON(!gmu->legacy); >> + >> + /* Nothing to do if GMU does the power management */ >> + if (gmu->idle_level > GMU_IDLE_STATE_ACTIVE) > > This isn't quite a no-op, but I can't seem to find what the '1' value > would map to, even in 845 kernel sources. Do we have to worry about it?
This is fine. '1' seems to be a low power state that was removed very early in the gmu firmware development stage. We can ignore that. -Akhil. > > Konrad
