On 7/22/2025 7:01 PM, Dmitry Baryshkov wrote: > On Sun, Jul 20, 2025 at 05:46:05PM +0530, Akhil P Oommen wrote: >> A7XX_GEN2 generation has additional TCS slots. Poll the respective >> DRV status registers before pm suspend. >> > > Fixes?
Ack. Will add the tag. It is good to ensure there are no outstanding votes. -Akhil > >> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> index >> 790ef2f94a0b0cd40433d7edb6a89e4f04408bf5..3bebb6dd7059782ceca29f2efd2acee24d3fc930 >> 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -987,6 +987,22 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) >> val, (val & 1), 100, 10000); >> gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, >> val, (val & 1), 100, 1000); >> + >> + if (!adreno_is_a740_family(adreno_gpu)) >> + return; >> + >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS5_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS6_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS7_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS8_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS9_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); >> } >> >> /* Force the GMU off in case it isn't responsive */ >> >> -- >> 2.50.1 >> >
