On Wed, Jul 23, 2025 at 01:22:20AM +0530, Akhil P Oommen wrote:
> On 7/22/2025 8:03 PM, Konrad Dybcio wrote:
> > On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> >> Bitfield definition for REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS register is
> >> different in A7XX family. Check the correct bits to see if GX is
> >> collapsed on A7XX series.
> >>
> >> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
> >> ---
> >
> > This seems to have been introduced all the way back in the initial
> > a7xx submission downstream, so I'll assume this concerns all SKUs
> > and this is a relevant fixes tag:
> >
> > Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support")
> >
> > Reviewed-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
>
> Dmitry/Konrad,
>
> We don't have to backport this change because the existing code reads a
> couple of unused bits which are '0's and that is okay when IFPC is not
> supported. So there is no practical benefit in cherry-picking this
> change to older kernel versions.
Fixes tag is not about backporting. It is to point out that there was an
issue in the original commit which is fixed by a new one.
>
> -Akhil.
>
> >
> > Konrad
>
--
With best wishes
Dmitry
