On Fri, 16 Jan 2026 13:57:31 +0100 Nicolas Frattaroli <[email protected]> wrote:
> The current IRQ helpers do not guarantee mutual exclusion that covers > the entire transaction from accessing the mask member and modifying the > mask register. > > This makes it hard, if not impossible, to implement mask modification > helpers that may change one of these outside the normal > suspend/resume/isr code paths. > > Add a spinlock to struct panthor_irq that protects both the mask member > and register. Acquire it in all code paths that access these, but drop > it before processing the threaded handler function. Then, add the > aforementioned new helpers: enable_events, and disable_events. They work > by ORing and NANDing the mask bits. > > resume is changed to no longer have a mask passed, as pirq->mask is > supposed to be the user-requested mask now, rather than a mirror of the > INT_MASK register contents. Users of the resume helper are adjusted > accordingly, including a rather painful refactor in panthor_mmu.c. > > In panthor_mmu.c, the bespoke mask modification is excised, and replaced > with enable_events/disable_events in as_enable/as_disable. > > Co-developed-by: Boris Brezillon <[email protected]> > Signed-off-by: Boris Brezillon <[email protected]> > Signed-off-by: Nicolas Frattaroli <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Just one question below. > --- > drivers/gpu/drm/panthor/panthor_device.h | 86 > ++++++++++++++++++++++++++------ > drivers/gpu/drm/panthor/panthor_fw.c | 3 +- > drivers/gpu/drm/panthor/panthor_gpu.c | 2 +- > drivers/gpu/drm/panthor/panthor_mmu.c | 47 ++++++++--------- > drivers/gpu/drm/panthor/panthor_pwr.c | 2 +- > 5 files changed, 98 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/panthor/panthor_device.h > b/drivers/gpu/drm/panthor/panthor_device.h > index 8597b388cc40..8664adb1febf 100644 > --- a/drivers/gpu/drm/panthor/panthor_device.h > +++ b/drivers/gpu/drm/panthor/panthor_device.h > @@ -84,9 +84,19 @@ struct panthor_irq { > /** @irq: IRQ number. */ > int irq; > > - /** @mask: Current mask being applied to xxx_INT_MASK. */ > + /** @mask: Values to write to xxx_INT_MASK if active. */ > u32 mask; > > + /** > + * @mask_lock: protects modifications to _INT_MASK and @mask. > + * > + * In paths where _INT_MASK is updated based on a state > + * transition/check, it's crucial for the state update/check to be > + * inside the locked section, otherwise it introduces a race window > + * leading to potential _INT_MASK inconsistencies. > + */ > + spinlock_t mask_lock; > + > /** @state: one of &enum panthor_irq_state reflecting the current > state. */ > atomic_t state; > }; > @@ -425,13 +435,14 @@ static irqreturn_t panthor_ ## __name ## > _irq_raw_handler(int irq, void *data) > if (!gpu_read(ptdev, __reg_prefix ## _INT_STAT)) > \ > return IRQ_NONE; > \ > > \ > + guard(spinlock_irqsave)(&pirq->mask_lock); > \ > + gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); > \ > old_state = atomic_cmpxchg(&pirq->state, > \ > PANTHOR_IRQ_STATE_ACTIVE, > \ > PANTHOR_IRQ_STATE_PROCESSING); > \ > if (old_state != PANTHOR_IRQ_STATE_ACTIVE) > \ > return IRQ_NONE; > \ > > \ > - gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); > \ Is moving this INT_MASK=0 before the atomic_cmpxchg() is really required. It's harmless of course, because of the lock surrounding the state + INT_MASK update, but I was wondering if there was another reason for doing that that I'm missing. > return IRQ_WAKE_THREAD; > \ > } > \
