On 3/24/2026 3:04 AM, Dmitry Baryshkov wrote: > On Tue, Mar 24, 2026 at 01:42:24AM +0530, Akhil P Oommen wrote: >> Adreno X2-85 series present in Glymur chipset supports a new mechanism >> for SKU detection. A new CX_MISC register exposes the combined (or >> final) speedbin value from both HW fuse register and the Soft Fuse >> register. >> >> Implement this new SKU detection along with a new quirk to identify the >> GPUs that has SOFT SKU support. Also, enable this quirk for Adreno X2-85 > > SOFT SKU -> Soft fuse? > >> and add its SKU table to the catalog. >> >> Signed-off-by: Akhil P Oommen <[email protected]> >> --- >> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 ++++ >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 9 +++++- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 41 >> ++++++++++++++++++++++----- >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ---- >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + >> drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4 +++ >> 6 files changed, 53 insertions(+), 13 deletions(-) >> >> @@ -1213,10 +1212,6 @@ int adreno_gpu_init(struct drm_device *drm, struct >> platform_device *pdev, >> devm_pm_opp_set_clkname(dev, "core"); >> } >> >> - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) >> - speedbin = 0xffff; >> - adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); >> - > > You have removed this from the generic code and then added it to a5xx > and a6xx+. Wouldn't this cause a change on a2xx - a4xx?
In the the devicetree, only a5x and a6x chipsets are users of the speed_bin cells. Also, I believe Mesa handles speedbin=0 correctly for A4x and older chipsets. So we can ignore those. -Akhil. > >> gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, >> ADRENO_CHIPID_ARGS(config->chip_id)); >> if (!gpu_name) >
