On 3/24/2026 3:48 PM, Konrad Dybcio wrote:
> On 3/23/26 9:12 PM, Akhil P Oommen wrote:
>> The programing sequence related to preemption is unchanged from A7x. But
>> there is some code churn due to register shuffling in A8x. So, split out
>> the common code into a header file for code sharing and add/update
>> additional changes required to support preemption feature on A8x GPUs.
>>
>> Finally, enable the preemption quirk in A840's catalog to enable this
>> feature.
>>
>> Signed-off-by: Akhil P Oommen <[email protected]>
>> ---
>
> [...]
>
>> + /* ... and after*/
>
> ultra nit: space before comment end marker, please
>
> [...]
>
>> +static int a8xx_preempt_start(struct msm_gpu *gpu)
>> +{
>> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> + struct msm_ringbuffer *ring = gpu->rb[0];
>> +
>> + if (gpu->nr_rings <= 1)
>
> Can this ever be < 1?
This is just copy-paste from a7xx_preempt_start().
>
>
>> +static void a8xx_preempt_keepalive_vote(struct msm_gpu *gpu, bool on)
>> +{
>> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> +
>> + if (adreno_has_gmu_wrapper(adreno_gpu))
>> + return;
>
> Are we going to have any a8xx+gmuwrapper?
We can remove that check.
-Akhil.
>
> Konrad
