On Don, 2002-09-26 at 18:17, Keith Whitwell wrote: > Michel Dänzer wrote: > > > > Something else I've been thinking about is that relying on the > > swi_emitted and swi_received counters being in sync is pretty fragile. > > It might be better to use a scratch register instead. > > Yes, it could be made more robust.
Do you think the approach with a scratch register is good? > > Moreover, nicod on IRC reports that IRQs stop working for him in the > > middle of glxgears running. So I thought let's make really really sure > > they are enabled in the DRM instead of doing it in the 2D driver and > > praying. The result is > > > > http://penguinppc.org/~daenzer/DRI/radeon-swi-scratch.diff > > > > but unfortunately, it doesn't seem to really help with the second issue. > > Can anyone think of a way how the IRQs can get disabled in the chip with > > this? Could writing to GEN_INT_CNTL too often actually hurt? Works fine > > here though... > > > > At least, with this patch it keeps running at about the same speed as > > with usleeps when the IRQs go nuts. > > We shoudl add diagnostics to the -EBUSY case in wait_irq to try and figure out > what has happened -- particularly have the interrupts been disabled? Turns out they haven't. GEN_INT_CNTL looks exactly like it should. Interestingly, the GEN_INT_STATUS bits are set as well, and acknowledging them helps. So it seems that somehow, the service routine didn't get called for an interrupt, or the acknowledgement got lost. If the updated patch works for you as well, I'll commit it. -- Earthling Michel Dänzer (MrCooper)/ Debian GNU/Linux (powerpc) developer XFree86 and DRI project member / CS student, Free Software enthusiast ------------------------------------------------------- This sf.net email is sponsored by:ThinkGeek Welcome to geek heaven. http://thinkgeek.com/sf _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
