On Fri, 2002-09-27 at 17:01, Michel Dänzer wrote: > > Yep, but I guess you have to worry about then going to sleep *after* the > > interrupt has arrived, if there is a delay in getting the scratch write across > > the bus, compared to the irq, which should be instantaneous. > > Is that really an issue? The scratch register is written to before the > interrupt is triggered, so I'd expect a register read to yield the > correct value when the interrupt has arrived.
Interrupt delivery on x86 is extremely asynchronous on some systems - especially Pentium II/Pentium III SMP boxes. You can sometimes see situations like IRQ raised driver clear irq allowed flag driver reads PCI bus to force posting driver free some resources IRQ arruves driver explodes In almost all cases PCI/IRQ synchronization isnt quite what you might intuitively wish for or expect. ------------------------------------------------------- This sf.net email is sponsored by:ThinkGeek Welcome to geek heaven. http://thinkgeek.com/sf _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
