Am Montag, 16. Dezember 2002 22:59 schrieb Brian Paul: > Andy Ross wrote:
> > Actually, I'm fuzzy on the spec here. The DRI (and NVidia) drivers > > appear to *not* sample the texture border color by default when > > drawing quads with texture coordinates of exactly 1 and 0. The ATI > > ones seem to do so, which results in a dark stripe between tiles > > (FlightGear doesn't bother to set the border color and leaves it as > > black). Problem is, my cursory reading of the spec says that ATI is > > right and the rest of the world (!) is wrong, even though that would > > make life hell for people who simply want to build up tiled images and > > don't care (much) about border artifacts. What's the truth? > > Texture borders are kinda complicated. You can either define an explicit > image border (glTexImage2D's border=1) or use the default texture border > color. Whether or not the texture border is sampled is determined by the > texture filter and wrap mode. There are lots of mode combinations, some > of which sometimes sample the border, and others which never do. > > Texture borders are an area that's still kind of flakey in today's drivers. > They've always been trouble. > > I've been pretty careful to get this right in Mesa's software rasterizer. > The Mesa/test/texwrap.c demo shows a bunch of different modes. And again. Current trunk (r200) only running with MESA_NO_SSE on Athlon/Duron. -Dieter Reading symbols from /usr/X11R6/lib/modules/dri/r200_dri.so...done. Loaded symbols for /usr/X11R6/lib/modules/dri/r200_dri.so #0 0x40610724 in _mesa_sse_transform_points2_3d_no_rot () from /usr/X11R6/lib/modules/dri/r200_dri.so (gdb) bt #0 0x40610724 in _mesa_sse_transform_points2_3d_no_rot () from /usr/X11R6/lib/modules/dri/r200_dri.so #1 0x081f5638 in ?? () #2 0x40524310 in default_calloc () from /usr/X11R6/lib/modules/dri/r200_dri.so #3 0xfffad7e8 in ?? () Cannot access memory at address 0x82474ff (gdb) disassemble Dump of assembler code for function _mesa_sse_transform_points2_3d_no_rot: 0x406106b8 <_mesa_sse_transform_points2_3d_no_rot>: push %esi 0x406106b9 <_mesa_sse_transform_points2_3d_no_rot+1>: push %edi 0x406106ba <_mesa_sse_transform_points2_3d_no_rot+2>: mov 0x14(%esp,1),%esi 0x406106be <_mesa_sse_transform_points2_3d_no_rot+6>: mov 0xc(%esp,1),%edi 0x406106c2 <_mesa_sse_transform_points2_3d_no_rot+10>: mov 0x10(%esp,1),%edx 0x406106c6 <_mesa_sse_transform_points2_3d_no_rot+14>: mov 0x8(%esi),%ecx 0x406106c9 <_mesa_sse_transform_points2_3d_no_rot+17>: test %ecx,%ecx 0x406106cb <_mesa_sse_transform_points2_3d_no_rot+19>: je 0x4061073c <_mesa_sse_transform_points2_3d_no_rot+132> 0x406106cd <_mesa_sse_transform_points2_3d_no_rot+21>: mov 0xc(%esi),%eax 0x406106d0 <_mesa_sse_transform_points2_3d_no_rot+24>: orl $0x7,0x14(%edi) 0x406106d4 <_mesa_sse_transform_points2_3d_no_rot+28>: mov %ecx,0x8(%edi) 0x406106d7 <_mesa_sse_transform_points2_3d_no_rot+31>: movl $0x3,0x10(%edi) 0x406106de <_mesa_sse_transform_points2_3d_no_rot+38>: shl $0x4,%ecx 0x406106e1 <_mesa_sse_transform_points2_3d_no_rot+41>: mov 0x4(%esi),%esi 0x406106e4 <_mesa_sse_transform_points2_3d_no_rot+44>: mov 0x4(%edi),%edi 0x406106e7 <_mesa_sse_transform_points2_3d_no_rot+47>: add %edi,%ecx 0x406106e9 <_mesa_sse_transform_points2_3d_no_rot+49>: nop 0x406106ea <_mesa_sse_transform_points2_3d_no_rot+50>: nop 0x406106eb <_mesa_sse_transform_points2_3d_no_rot+51>: nop 0x406106ec <_mesa_sse_transform_points2_3d_no_rot+52>: nop 0x406106ed <_mesa_sse_transform_points2_3d_no_rot+53>: nop 0x406106ee <_mesa_sse_transform_points2_3d_no_rot+54>: nop 0x406106ef <_mesa_sse_transform_points2_3d_no_rot+55>: nop 0x406106f0 <_mesa_sse_transform_points2_3d_no_rot+56>: nop 0x406106f1 <_mesa_sse_transform_points2_3d_no_rot+57>: nop 0x406106f2 <_mesa_sse_transform_points2_3d_no_rot+58>: nop 0x406106f3 <_mesa_sse_transform_points2_3d_no_rot+59>: nop 0x406106f4 <_mesa_sse_transform_points2_3d_no_rot+60>: nop 0x406106f5 <_mesa_sse_transform_points2_3d_no_rot+61>: nop 0x406106f6 <_mesa_sse_transform_points2_3d_no_rot+62>: nop 0x406106f7 <_mesa_sse_transform_points2_3d_no_rot+63>: nop 0x406106f8 <_mesa_sse_transform_points2_3d_no_rot+64>: nop 0x406106f9 <_mesa_sse_transform_points2_3d_no_rot+65>: nop 0x406106fa <_mesa_sse_transform_points2_3d_no_rot+66>: nop 0x406106fb <_mesa_sse_transform_points2_3d_no_rot+67>: nop 0x406106fc <_mesa_sse_transform_points2_3d_no_rot+68>: nop 0x406106fd <_mesa_sse_transform_points2_3d_no_rot+69>: nop 0x406106fe <_mesa_sse_transform_points2_3d_no_rot+70>: nop 0x406106ff <_mesa_sse_transform_points2_3d_no_rot+71>: nop 0x40610700 <_mesa_sse_transform_points2_3d_no_rot+72>: movss 0x0(%edx),%xmm1 0x40610705 <_mesa_sse_transform_points2_3d_no_rot+77>: movss 0x14(%edx),%xmm2 0x4061070a <_mesa_sse_transform_points2_3d_no_rot+82>: unpcklps %xmm2,%xmm1 0x4061070d <_mesa_sse_transform_points2_3d_no_rot+85>: movlps 0x30(%edx),%xmm2 0x40610711 <_mesa_sse_transform_points2_3d_no_rot+89>: movss 0x38(%edx),%xmm3 0x40610716 <_mesa_sse_transform_points2_3d_no_rot+94>: lea 0x0(%esi),%esi 0x40610719 <_mesa_sse_transform_points2_3d_no_rot+97>: lea 0x0(%edi,1),%edi 0x40610720 <_mesa_sse_transform_points2_3d_no_rot+104>: movlps 0x0(%esi),%xmm0 0x40610724 <_mesa_sse_transform_points2_3d_no_rot+108>: mulps %xmm1,%xmm0 0x40610727 <_mesa_sse_transform_points2_3d_no_rot+111>: addps %xmm2,%xmm0 0x4061072a <_mesa_sse_transform_points2_3d_no_rot+114>: movlps %xmm0,0x0(%edi) 0x4061072e <_mesa_sse_transform_points2_3d_no_rot+118>: movss %xmm3,0x8(%edi) 0x40610733 <_mesa_sse_transform_points2_3d_no_rot+123>: add $0x10,%edi 0x40610736 <_mesa_sse_transform_points2_3d_no_rot+126>: add %eax,%esi 0x40610738 <_mesa_sse_transform_points2_3d_no_rot+128>: cmp %ecx,%edi 0x4061073a <_mesa_sse_transform_points2_3d_no_rot+130>: jne 0x40610720 <_mesa_sse_transform_points2_3d_no_rot+104> 0x4061073c <_mesa_sse_transform_points2_3d_no_rot+132>: pop %edi 0x4061073d <_mesa_sse_transform_points2_3d_no_rot+133>: pop %esi 0x4061073e <_mesa_sse_transform_points2_3d_no_rot+134>: ret 0x4061073f <_mesa_sse_transform_points2_3d_no_rot+135>: nop End of assembler dump. ------------------------------------------------------- This sf.net email is sponsored by: With Great Power, Comes Great Responsibility Learn to use your power at OSDN's High Performance Computing Channel http://hpc.devchannel.org/ _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel