> > Which would exactly fit between 0xCFFE0000 - 0xCFFFFFFF. Yes this is an > assumption, but some of the DRI code mentions that PCI express allocates the > GART table at the end of the frame buffer, so that is why I was thinking it > worked this way.
Can you dump that memory area? see if it has a GART table in it.. GART tables usually are fairly easy to spot lots of page pointers.. > > Ok.. I read that file. None of them seem to touch the card directly.. The > only bits that I found which actually touch the card are in radeon_cp.c (at > least the older git checkout that I have...) ati_pcigart.c just creates the tables, the registers to poke are differrent depending on the type of gart.. > > When you say that the card reacts, are you referring to tickling these > registers: RADEON_AIC_CNTL, RADEON_AIC_PT_BASE, RADEON_AIC_LO_ADDR, > RADEON_AIC_HI_ADDR? (none of my fglrx traces (libsegfault or kmmio) touch > these registers...) Yeah I just tried to see if a PCI GART worked, I didn't care if fglrx used it or not,... there is probably something else necessary outside the normal setup regs to get it to work I gave it up on it when it didn't work out of the box.. Dave. ------------------------------------------------------------------------- Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT & business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.php&p=sourceforge&CID=DEVDEV -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
