Digital designer ask me about interfce model of my analog IP core. He need this due to add model of interface inputs/outputs core to system simulation. Generally digital designers considering that as using back aannotaed post-synth or post-layout model (likes logic effort estimation of delays in pure digital system).
In fact he is inerested to make his simu;ation tools (like Modelsim) to know load characteristics of IO pins of analog "BlackBox". (This may include parasitics or not. Even without parasitic it is usefull information for test automation of digital part) Realistic Spice like simulation is NOT a point of interest of a digital designer. Do we currently have any functionalyty in Electric which can generate logic effort like RTL model likes AMS Verilog or either? Or appropriate point to extend somt other functionality to this ...??? On 8/17/18, Alexandre Rusev <[email protected]> wrote: > > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
