-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 2/13/2013 11:52 AM, Michael Haberler wrote: > > Am 13.02.2013 um 18:47 schrieb Eric Keller: > >> On Wed, Feb 13, 2013 at 12:29 PM, Michael Haberler >> <mai...@mah.priv.at>wrote: >> >>> the hlt instruction doesn't work correctly
The hlt instruction works fine, it just doesn't mesh well with real-time systems and deterministic latency. >> It bugs me that in these days of high performance and energy >> aware computers that the hlt command apparently doesn't work >> properly on a lot of processors. This affects realtime users the >> most, but it surely reduces the usability of all computers. I >> guess they figure we keep buying computers and they can sell us >> whatever they want. > > well I dont know enough about how the electronics of all this is > implemented, but if any of the power supply (like onboard SMPS > regulators) is involved in the CPU voltage reduction of some of > these C* states, I wouldnt be suprised that cranking up to full > voltage does take some time, 'some' being rather long and rather > indeterministic in the context of an RT application > > it is pure conjecture though > > anybody here who can comment on CPU voltage reduction and how that > is done? > > that could also explain different board behavior At my work, we had to chase down issues related to the power states for our real-time (video streaming and editing) application. We were doing bus-mastering PCIe transfers direct to memory, but when the CPU was changing power modes, it would block *EVERYTHING* (even our DMA data transfers that weren't using the CPU at all) in order to maintain cache coherency while the CPU was off-line. The issue didn't really seem to be based around power supply voltages, although I'm sure some of the newer (and particularly the mobile) chips probably make use of that. In the desktop parts we were using, the transition times were apparently based on lock times for the various internal PLLs as the CPU operating frequency jumped around. If memory serves, there was an external signal that indicated the chipset should hold off on any writes to main memory, which might be a signal you could 'scope. I don't off-hand recall the signal name, and I'm sure it's changed a few times since then (this was maybe 3 CPU generations ago, the early Core architecture parts IIRC). - -- Charles Steinkuehler char...@steinkuehler.net -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (MingW32) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iEYEARECAAYFAlEb6Y4ACgkQLywbqEHdNFw7SACcDck16kOZKzCempMrQs2yovE5 7SoAn06ouixTXYnBL16hRdNWte6WKvbv =yFdS -----END PGP SIGNATURE----- ------------------------------------------------------------------------------ Free Next-Gen Firewall Hardware Offer Buy your Sophos next-gen firewall before the end March 2013 and get the hardware for free! Learn more. http://p.sf.net/sfu/sophos-d2d-feb _______________________________________________ Emc-developers mailing list Emc-developers@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-developers
