Correct, the picture is complex. The PCB is 2-layer with signal, 5V-power and 0V-ref lines routed on both sides. There is no ground layer/plane. There must be a large number of RF current loops because the 0V-lines are routed up and down and around. Beside trying to achieve a good decoupling I assume that reducing loop area is the most important.
Amund -----Opprinnelig melding----- Fra: Cortland Richmond [mailto:72146....@compuserve.com] Sendt: 18. april 2002 00:54 Til: am...@westin-emission.no; ieee pstc list Emne: Re: Decoupling - capacitor values Yes, it makes sense. But the goal here is preventing or reducing Vcc drop during the time the microprocessor is switching. You need not only low reactance, but *also* enough capacitance to supply the current needed _while it is switching_. You have not given enough information here to tell if 820pF is sufficient. Regards, Cortland Richmond Amund Westin wrote: >> Insert a SMD ceramic capacitor of value 820pF in parallel with the existing 100nF. The reason for the low value 820pF is because the capacitor self-resonance frequency is approximate 180MHz, and I believe it is important to choose a Cap value with a resonance frequency higher than the frequency we would like to decouple. Does it make sense? << ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on "browse" and then "emc-pstc mailing list"
