Amund,
In the absence of any layout information that can evaluate the loop
inductances, I suggest you read what I wrote about placing two capacitor in
parallel which can be found on Chapter 3 of my thesis.  A link is available
in:

http://www.geocities.com/timfoo6143/index.html

BTW, how about just using a 100 pF capacitor with the 'leads' hugging close
to the microprocessor package.  i.e. assuming you are using a leaded
capacitor (on say a QFP).

:-)

Tim Foo


                                                                                
                                                           
                      amund@westin-emission.                                    
                                                           
                      no                             To:      
<emc-p...@majordomo.ieee.org>                                                
                      Sent by:                       cc:      (bcc: Wan Juang 
Foo/ece/staff/npnet)                                         
                      owner-emc-pstc@majordo         Subject: Decoupling - 
capacitor values                                                
                      mo.ieee.org                                               
                                                           
                                                                                
                                                           
                                                                                
                                                           
                      04/18/02 04:49 AM                                         
                                                           
                      Please respond to                                         
                                                           
                      amund                                                     
                                                           
                                                                                
                                                           
                                                                                
                                                           





A microprocessor is driven by a 12MHz clock. The 5V Vcc-pin is decoupled by
a 100nF capacitor with a few mm leads. We can observe an unwanted 156MHz
signal on the 5V line, maybe 13th harmonic of 12MHz. We will try to
suppress/decouple this 156MHz signal.

Suggestion:
Insert a SMD ceramic capacitor of value 820pF in parallel with the existing
100nF. The reason for the low value 820pF is because the capacitor
self-resonance frequency is approximate 180MHz, and I believe it is
important to choose a Cap value with a resonance frequency higher than the
frequency we would like to decouple.

Does it make sense?

Best regards
Amund Westin, Oslo/Norway



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