On Tue, 1 May 2007, Seb James wrote:

> Date: Tue, 01 May 2007 15:28:43 +0100
> From: Seb James <[EMAIL PROTECTED]>
> Reply-To: "Enhanced Machine Controller (EMC)"
>     <emc-users@lists.sourceforge.net>
> To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge.net>
> Subject: Re: [Emc-users] Newest 5i20 FPGA code
> 
> On Tue, 2007-05-01 at 07:06 -0700, Peter C. Wallace wrote:
>> On Tue, 1 May 2007, Seb James wrote:
>>
>>> Date: Tue, 01 May 2007 14:26:35 +0100
>>> From: Seb James <[EMAIL PROTECTED]>
>>> Reply-To: "Enhanced Machine Controller (EMC)"
>>>     <emc-users@lists.sourceforge.net>
>>> To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge.net>
>>> Subject: Re: [Emc-users] Newest 5i20 FPGA code
>>>
>>> On Tue, 2007-05-01 at 08:56 -0400, John Kasunich wrote:
>>>> Seb James wrote:
>>>>> Hi List,
>>>>>
>>>>> This message is about the latest 5i20 FPGA code which John Kasunich said
>>>>> he was working on in February this year (around then anyhow).
>>>>>
>>>>> The feature in this new code which I need is the ability to configure
>>>>> the 5i20 with between 0 and 8 axes of (pwm)servo outputs and encoder
>>>>> inputs with the rest of the 5i20 I/O being used as simple logic inputs
>>>>> and outputs.
>>>>>
>>>>> In my case, the servo/encoder i/o will be routed through a Mesa 7i33
>>>>> board for signal conditioning.
>>>>>
>>>>> Has this new code made its way into a release yet? I'm going to check
>>>>> out the CVS EMC2 version and have a look in there right now. None of the
>>>>> changelogs say anything about this code in a release, so I guess it
>>>>> hasn't been released yet.
>>>>>
>>>>> I'm going to try to make use of the code, so I may have some questions
>>>>> for the list!
>>>>
>>>> My stuff isn't there yet.  I have been getting bogged down in a bunch
>>>> of "infrastructure" issues having to do with managing various FPGA
>>>> configurations.  In addition, my first target is step generators.
>>>>
>>>> However, I believe the existing "hostmot5-8" configuration will meet
>>>> your needs.  For some notes, see:
>>>> http://cvs.linuxcnc.org/cgi-bin/cvsweb.cgi/emc2/src/hal/drivers/m5i20/README.txt?rev=1.3
>>>>
>>>> That config is not part of the version 2.1.4 release - you'll need to
>>>> get a CVS checkout to use it.  It will be in 2.2.0 however.
>>>>
>>>
>>> I've been having a look at the emc2-trunk source tree. Is your new stuff
>>> going in emc2-trunk/src/hal/drivers/mesa_5i2x?
>>>
>>> I think the hostmot5-8 configuration will be close to what I require for
>>> one of my boards (we're doing a simple 2 axis machine with one 5i20 then
>>> we'll move on to the 9 axis machine which requires 4 5i20 boards). Does
>>> the hostmot5-8 configuration bind 5i20 pins to particular servo/encoder
>>> functions? By that I means would hostmot5-8 fix, say, pin 25 to be a
>>> servo pwm direction output?
>>>
>>> Initially I need a configuration which has exactly two servo/encoder
>>> axes (12 pins in all), 31 logic inputs and 29 logic outputs.
>>>
>>> I think I need to write a new VHDL configuration for this setup. Would
>>> you agree?
>>>
>>> Seb
>>>
>>
>> If someone would write a updated driver, I have a 12 axis servo configuration
>> with servo outputs overlaid on I/O (so if they are not enabled you have 72 
>> bit
>> of I/O). This is not a fancy as John K's, but the pinout definition is just a
>> little section that wires the servo pins to I/O pins so the pinout is easy to
>> change plus, if you can live with the existing pinout, it can easily be
>> programmed to do what you want by just enabling 2 servo axis (leaving 60 pins
>> as I/O)
>
> Hi Peter,
>
> Does this "configuration with servo outputs overlaid on I/O" place any
> limit on the rate at which a pwm can be generated? Not that I am too
> worried about this, so long as these outputs can drive your 7I33 board.

The PWM generators have been simplified (no signed/unsigned mode) but have a 
resolution mask so they can be 8/9/10/11/12 bits. Base PWM rate is 100 MHz so 
10 bit PWM goes up to ~100 KHz, 12 bit up to ~25 KHz. Symmetrical PWM mode is 
supported (for 3 phase AC or 2 phase AC for (variable) voltage mode step motor 
drive) . No problem with 7I33 card.


>
> What do you mean by an updated driver? What changes need to be made in
> the driver? Is the work that John K has been doing on a new driver going
> to fit the bill?

This is updated so its all 32 bit access, bus interface has been cleaned up 
and supports burst mode access. Just added wait state support so 50 MHz local 
bus is supported (Requires added surface mount 0 Ohm "resistors" on 5I20)

Quadrature counters can be the same as old (32 bit count) or new version that 
John K suggested with 16 bit counter and 16 bit "last encoder edge" timestamp 
for less "crunchy" velocity measurement at low speeds.

>
> When you say "this is not as fancy as John K's" do you mean that your
> configuration is not as fancy as the hostmotXXX configurations which are
> in the emc2 cvs trunk?

No, not as fancy as Johns auto build and driver hardware capability 
detect/setup stuff.


>
>> Also we are coming out with a USB/SPI I/O expander with 24 isolated inputs 
>> and
>> 24 isolated outputs. This can use 6 pins on a 50 pin interface connector, 
>> (SPI
>> mode) allowing 4 expanders to share a 50 pin cable. If you are using isolated
>> I/O this could save a lot of 5I20 I/O pins.
>
> That sounds interesting, but I have just had some great big pcbs made up
> with 12 50 pin IDCs on to connect to an array of 4 of your 5I20 boards!
>
> Seb

OK...

>
>
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Peter Wallace
Mesa Electronics

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