On Thu, 4 Dec 2008, Eric H. Johnson wrote:
> Date: Thu, 4 Dec 2008 19:49:12 -0500
> From: Eric H. Johnson <[EMAIL PROTECTED]>
> Reply-To: "Enhanced Machine Controller (EMC)"
> <emc-users@lists.sourceforge.net>
> To: "'Enhanced Machine Controller (EMC)'" <emc-users@lists.sourceforge.net>
> Subject: [Emc-users] Write error with hostmot2 and 7i43 board
>
> Sebastian, et al,
>
> I am getting a strange error using the hostmot2 driver and the 7i43 board.
> The error is "hm2/hm2_7i43.0: TRAM write error! (addr=0x1000, size=8,
> iter=68373). The error occurs when running a g-code program but not while
> jogging, at least initially.
>
> If I bring the system up from a fresh boot, I can jog. But once I run a
> g-code program and get the error, I will then get a following error if I try
> to jog an axis. Additionally, if I shut down the program and restart,
> immediately after coming up again I get an error "hm2_7i43:/DONE is not low
> after CPLD reset!
>
> Except for remapping some of the GPIO (which is currently mostly disabled)
> and of course the bit file specified, the configuration is identical to my
> working configuration on the m5i20 controller. I get the same error and
> symptoms for both SVST4_4B.BIT and SVST4_6B.BIT.
>
> I gather it has something to do with the communications over the parallel
> port, but not sure what if any parameters affect that.
>
> Any ideas?
>
> Thanks,
> Eric
Well, Sebastian confirmed that the TRAM write error is an EPP timeout error,
but the CPLD error indicates something more global is wrong. Is it possible
you have a power supply issue?
EPP timeout means that the card did not respond to a address or data strobe by
de-asserting /Wait within 10 uSec. Normal FPGA timing is 300 nS for this time,
more than 10 Usec likely means that the card is unplugged, powered down or
some how locked-up. The CPLD error when attempting to re-program the FPGA
makes some kind of power or lock-up problem more likely the culprit.
What would be helpful to me is this information:
What are the LED states when you get the TRAM error?
What are the LED states when you get the CPLD error?
When you say fresh boot, are you cycling the power?
Does reset without cycling the power allow you to reprogram the FPGA?
Peter Wallace
Mesa Electronics
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