uOn Sat, 3 Jan 2009, Gene Heskett wrote: SNIP_______________
>> > As a matter of fact, yes. The quad core amd phenoms, (I have a slow one in > this box) with some additional controls in the kernel to release one core > just for the realtime stuff, and then hand that core to rtai, seems like it > might be a pretty ideal situation. The only latency problem I could see > would be in freeing up the buss when it needs to access the parport, some > method of freezing the other 3 cores in their tracks for a couple of cpu > cycles might have to be worked out. > > Either that, or do a 'propeller' board for that part, in which case the base > loop could probably go away. > > I've been looking at that chip since it came out, has anyone here played with > it yet? > A perhaps more interesting chip for current "hardware replaced by software" designs is the 4 core XMOS (XS1-G4) with 4x 400 MHz cores each with 8 hardware contexts, about $20 for 1 piece (144 pin) and a $99 devkit. Kind of Ubicom on steroids... On the other hand you can do a lot with a embedded 32 bit processor in a FPGA (the ZPU for example uses about 20% of a 400K SP3, runs at ~ 100 MHz, is BSD licensed and has a GCC toolchain) SNIP____________________ Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your (")_(") signature to help him gain world domination. ------------------------------------------------------------------------------ _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users