Gene Heskett wrote: >[snip] > >>On the other hand you can do a lot with a embedded 32 bit processor in a >>FPGA (the ZPU for example uses about 20% of a 400K SP3, runs at ~ 100 MHz, >>is BSD licensed and has a GCC toolchain) >> >> > >Which again, sounds like a plus till you said 100mhz. That might do for servo >driven machines but I'd guess it won't run steppers at usable speeds will it? > > Apparently you missed the point that this is a processor embedded in an FPGA, so presumably you'd have the hardware needed for fast step generation, PWM, encoder counting, etc.
- Steve >[snip] > >If I was awake, its too late now for me, I might carve up a message to lkml, >and see if anyone has an idea of how much trouble it might be to pretend a 4 >core phenom is a 3 core chip, and hand the 4th core to rtai, operating not in >a sandbox cuz that would deny hdwe access, but I'd think something along >those lines could be put together, and probably without major surgery to the >core smp code linux now has. > Linux and RTAI support isolated CPUsets. You can tell Linux to not schedule process on certain cores, and then tell RTAI to bind processes to those cores. EMC2 already does this by default when compiled on SMP machines, though you do need to supply the correct boot parameters to the kernel. In practice, I haven't seen a great improvement from simply going to a multi-core CPU. I haven't tested every machine out there though, so who knows. - Steve ------------------------------------------------------------------------------ _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
