Let's take the case of a 5i20 board running hostmot2. hostmot2 uses a DDS algorithm and tracks the low 16 bits of the step count.
Every servo cycle emc reads the step count from the board then sends a new frequency command to the board. hostmot2 uses a DDS algorithm based on a 33MHz clock. This makes the absolute maximum step rate 16MHz (one clock HIGH, one clock LOW). In order to be able to accurately extend the step count from 16 bits to 64 bits, the delta between consecutive samples can be at most 32767. But with a 1ms servo period, the limit that this imposes is about 32MHz, so the original 16MHz limit is more limiting. But if you were to run with a markedly slower servo period, it could become a limiting factor (e.g., with a 5ms servo period this imposes a limit around 6MHz) The main limit is the minimum step period. Step space and length are rounded up to hostmot2 clocks, 30ns. For example, a timing of 10us will be rounded up to 334 clocks or 10.02us, and a timing of 15us will be exactly 500 clocks. So if you have a steplen of 15 and stepspace of 10, you'll actually get a minimum step time of 25.02us and a maximum step rate of just under 40kHz. In practice I'd knock a few percent off this number. For instance, itter can cause the requested step rate to vary a little in both directions, as the number of steps reported from the previous cycle varies a bit from what would be seen if the realtime performance was ideal. Jeff ------------------------------------------------------------------------------ This SF.Net email is sponsored by the Verizon Developer Community Take advantage of Verizon's best-in-class app development support A streamlined, 14 day to market process makes app distribution fast and easy Join now and get one step closer to millions of Verizon customers http://p.sf.net/sfu/verizon-dev2dev _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
