Re: [Flexradio] frequency calibration etc

[ecellison]

Folks   I have a stupid question which I should be able to look up. Can an FPGA pin actually accept a 10 mhz or 200 mhz signal so that the LE’s could be configured to divide it down?   I really do like Bob’s example and suggestion. Have 1 10 mhz tcvcxo interfaced to the GPS and stabilized. Divide the 200 mhz signal down to say 10 meg compare the reference sig to the LO and tell the software to correct for variance in the 200 mhz LO. Am I understanding this correctly. (forget whether it is a PIC or FPGA or discrete hardware).   I need a block diag to follow all this (smile). It’s fun tho!   Eric     From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] On Behalf Of Jeff Anderson Sent: Wednesday, November 23, 2005 12:04 PM To: Jim Lux; [EMAIL PROTECTED] Biz Subject: Re: [Flexradio] frequency calibration etc   Hi Jim, Jim Lux <[EMAIL PROTECTED]> wrote: Or, use a fixed oscillator, and run an NCO in the FPGA to create an offset frequency, which you then mix with the fixed oscillator to create your locked output. [This is what we are doing in an experimental deep space transponder.. where phase noise is of obssessive concern]   [WA6AHL] : I like your idea.  But let me see if I understand it...in an app such as, say, a general-purpose way of generating a stable frequency using the Jupiter 1pps as reference, are you saying that the NCO (with an external, stable, oscillator as its clock source) would, in essence, be the digital version of the preiously mentioned VCO?  Phase comparison between the NCO's output and the reference 1pps is done within the FPGA and the error used to "steer" the NCO and proved an output that's locked to the ref?   Is one of the tradeoffs low phase-noise vs. frequency-step "quantization" of the NCO?  (E.g. the NCO might never be *exactly* on frequency).   In an application specific to the SDR1K, per Bob's example, you don't need the NCO.  Instead, feed the error sig back to the SDR1K and let s/w handle frequency correction...   > Or...you could even attempt loop >filtering within the fpga and generate the VCO control voltage a number of >ways - drive a dac, for example (similar to Shera's design - which I use >here to drive an HP 106B, by the way). But no matter which route is >followed, much attention needs to be paid to ground & power routing, layout, >etc, >to ensure that minimal noise is added to the VCO control voltage from >external sources. Which is precisly why I like the idea of measuring the offset and compensating in other ways, rather than steering the oscillator itself. Then, you can work on getting the best possible performance from the oscillator, which can be highly isolated from the outside world.   [WA6AHL]  Agreed.  Of course, depending upon how sensitive to noise your application is, good layout & bypassing techniques still apply even for the NCO technique.  Given finite slew-rates of digital signals, ground bounce or supply sag can increase switching-threshold uncertainty, resulting in jitter in the digital domain. Jim Lux <[EMAIL PROTECTED]> wrote: At 05:14 AM 11/23/2005, Jeff Anderson wrote: >Hi Eric - > >To your earlier post regarding implementing within an FPGA the circuitry >Alberto pointed to. Yes, this is easily done. In fact, I'd think you could >improve upon the design, too. For example, in the schematic you really >don't want the 43K resistor across the 470 uF cap - it, in series with the >15k resistor, will continually discharge the cap, meaning that the VCO >control voltage (and thus frequency) will continually vary as the cap >discharges and the phase-comparator pumps it back up to regain phase-lock. >Ideally, if you're in lock, you would like the control voltage to be an >unvarying DC level. Turning the first order loop into a second order loop. A first order loop will always have some small phase error, but it will be reasonably constant (frequency dependent, possibly). >Anyway - you could certainly implement all the digital circuitry as well as >a '4046-style phase comparator within the fpga and drive an external loop >filter, similar to shown in the schematic. Or, use a fixed oscillator, and run an NCO in the FPGA to create an offset frequency, which you then mix with the fixed oscillator to create your locked output. [This is what we are doing in an experimental deep space transponder.. where phase noise is of obssessive concern] > Or...you could even attempt loop >filtering within the fpga and generate the VCO control voltage a number of >ways - drive a dac, for example (similar to Shera's design - which I use >here to drive an HP 106B, by the way). But no matter which route is >followed, much attention needs to be paid to ground & power routing, layout, >etc, >to ensure that minimal noise is added to the VCO control voltage from >external sources. Which is precisly why I like the idea of measuring the offset and compensating in other ways, rather than steering the oscillator itself. Then, you can work on getting the best possible performance from the oscillator, which can be highly isolated from the outside world. >- Jeff, WA6AHL Jim, W6RMK