At 02:10 PM 6/9/01 +1000, Geoff Harland wrote:
>I currently check my PCB file visually to look for instances of items on
>Silkscreen layers being in locations they shouldn't be, and follow up by
>also checking the Gerber files in a similar manner. However I still
>appreciate that a Process that could detect and report such instances would
>have much to be said for it. And perhaps there is something to be said for
>enabling the user to optionally specify that silkscreen ink must also always
>be placed on top of soldermask material.
Yes. (1) Detect silkscreen ink within rule-defined distance of specified
objects. Usually this would be pads. Silkscreen on vias is relatively harmless.
(Whenever a rule specifies a clearance, negative clearance should be
recognised to allow specifying a limited overlap, by the way. This would
also fix the component clearance problem; the overlap would be set equal to
the width of outline track.)
(2) Detect silkscreen ink wherever no solder mask exists. Perhaps. This is
less important, because the major need -- to keep the ink off of pads -- is
addressed by the first suggestion.
(Years ago, we used to specify "no solder mask in holes," or "pads must be
clear of solder mask within 5 mils of holes." Solder-mask pad overlap --
for through-hole design -- was sometimes allowed. Solder mask on pads
becomes much more of a problem with SMT soldering. Mask on pad was allowed
because of registration difficulties. With relatively fine-line design, it
was necessary to specify tight mask blowout; a little misregistration might
put mask on a pad; if this was due to misregister, and there was even a
little pad on one side for the solder to bite -- with a full pad on the
other --, it was harmless.)
>I'm still working on writing software for a PCB Inverting Server, but I
>would consider creating such a Process after completing that. (I think that
>another task that such a Process should detect and report is incidents of
>silkscreen ink occupying the same area as items on the *Paste* Mask layer.
>You do not want silkscreen ink in any location where Solder Paste is being
>applied either.)
By definition, solder paste is applied where there is no mask, so the
silkscreen/solder mask rules would cover it. But once we are setting up
more flexible design rules -- which is surely desireable -- might as well
have the option of checking things like this. I'd like to be able to detect
object collision on mech layers.
Increasingly the design rules are getting more complex. This sets traps for
new users. I'd suggest a technology review DRC that would examine the
design rules and identify rules that would allow or create
difficult-to-fabricate boards (i.e., very fine line or clearances, tight
power plane clearances, etc.) and make suggestions as to how to improve
manufacturability. At least it should warn the user that he is making
things difficult for the fabricator, and thus for his or his company's
wallet. Perhaps sets of design rules could be compiled that would represent
different producibility levels, as per the IPC standards, so a new user
starts out with reasonable assumptions. OrCAD Layout has something like
this, I think.
PCAD has parametric rules, I believe. You can specify clearances by
voltage, or track width by current, if I understand this correctly.
Essentially this boils down to some built-in calculators, automatically
applied. I'd not be surprised to see something like this coming into Protel.
[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
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