https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81357
--- Comment #3 from Qing Zhao <qing.zhao at oracle dot com> ---
the zero extension "uxtw" insn is generated even without any optimiation, the
additional "mov" insn generated in -O2 is introduced by -fschedule-insns,
please see the following:
***/home/qinzhao/Install/latest/bin/gcc t.c
test1:
sub sp, sp, #16
str w0, [sp, 12]
ldr w0, [sp, 12]
add w0, w0, 1
uxtw x1, w0
adrp x0, d
add x0, x0, :lo12:d
str x1, [x0]
ldr w0, [sp, 12]
add w0, w0, 1
add sp, sp, 16
ret
***/home/qinzhao/Install/latest/bin/gcc -O t.c
test1:
add w0, w0, 1
uxtw x2, w0
adrp x1, d
str x2, [x1, #:lo12:d]
ret
***/home/qinzhao/Install/latest/bin/gcc -O -fschedule-insns t.c
test1:
add w1, w0, 1
adrp x2, d
mov w0, w1
uxtw x1, w1
str x1, [x2, #:lo12:d]
ret
So,
1. the zero extension comes from the language standard naturally. for aarch64,
due to the fact that the register W0 to X0 implicitly zero extension, the
explicitly zero extension insn can be optimized by some peephole optimization I
think.
2. will study why insn scheduler introduced the additional mov insns.
