https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81357
Wilco <wdijkstr at arm dot com> changed:
What |Removed |Added
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CC| |wdijkstr at arm dot com
--- Comment #7 from Wilco <wdijkstr at arm dot com> ---
(In reply to Qing Zhao from comment #5)
> Not sure why when -fschedule-insns is ON, the destination of the add insns
> becomes W1?
add w1, w0, 1
mov w0, w1
uxtw x1, w1
That's because the move assigns the return value which overwrites w0. However
the uxtw still needs to read the result of the addition. So the register
allocator is forced to use w1 as w0 cannot be used.
I don't think there is an easy fix for this example. The compiler believes
there are 2 distinct values so it uses 2 registers irrespectively of the order
of the mov and uxtw.
