https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81357
--- Comment #4 from Wilco <wilco at gcc dot gnu.org> ---
(In reply to Qing Zhao from comment #3)
> 1. the zero extension comes from the language standard naturally. for
> aarch64, due to the fact that the register W0 to X0 implicitly zero
> extension, the explicitly zero extension insn can be optimized by some
> peephole optimization I think.
>
> 2. will study why insn scheduler introduced the additional mov insns.
The scheduler didn't introduce an additional move. There are 2 distinct values
here, the 32-bit value fParm + 1 and the 64-bit zero-extended version of it.
Your example shows it perfectly:
add w1, w0, 1
mov w0, w1
uxtw x1, w1
The mov and uxtw are in fact the same instruction, however they are different
in the intermediate code. Due to being different operations the register
allocator needs 2 registers.
