[Bug target/99195] Optimise away vec_concat of 64-bit AdvancedSIMD operations with zeroes in aarch64

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99195

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkac...@gcc.gnu.org>:

https://gcc.gnu.org/g:12fae1f7fbe4df554bb257f805d9d324e276ab57

commit r14-423-g12fae1f7fbe4df554bb257f805d9d324e276ab57
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date:   Wed May 3 11:17:28 2023 +0100

    aarch64: PR target/99195 annotate HADDSUB patterns for vec-concat with zero

    Further straightforward patch for the various halving intrinsics with or
without rounding, plus tests.
    Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

    gcc/ChangeLog:

            PR target/99195
            * config/aarch64/aarch64-simd.md (aarch64_<sur>h<addsub><mode>):
Rename to...
            (aarch64_<sur>h<addsub><mode><vczle><vczbe>): ... This.

    gcc/testsuite/ChangeLog:

            PR target/99195
            * gcc.target/aarch64/simd/pr99195_1.c: Add tests for halving and
rounding
            add/sub intrinsics.