[Bug target/114734] [11/12/13/14/15 regression] RISC-V rv64gcv_zvl256b miscompile with -flto -O3 -mrvv-vector-bits=zvl since r8-6047-g65dd1346027bb5

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114734

--- Comment #12 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Biener <rgue...@gcc.gnu.org>:

https://gcc.gnu.org/g:4d3a5618de5a949c61605f545f90e81bc0000502

commit r15-60-g4d3a5618de5a949c61605f545f90e81bc0000502
Author: Richard Biener <rguent...@suse.de>
Date:   Fri Apr 26 15:47:13 2024 +0200

    middle-end/114734 - wrong code with expand_call_mem_ref

    When expand_call_mem_ref looks at the definition of the address
    argument to eventually expand a &TARGET_MEM_REF argument together
    with a masked load it fails to honor constraints imposed by SSA
    coalescing decisions.  The following fixes this.

            PR middle-end/114734
            * internal-fn.cc (expand_call_mem_ref): Use
            get_gimple_for_ssa_name to get at the def stmt of the address
            argument to honor SSA coalescing constraints.