[Bug target/128162] [17 Regression] wrong code at -O2: vwmacc.vx whose source is the upper half of the accumulator raises SIGILL

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128162

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:a8f38d8ca0185580d7c0944809e16e6ba5d0e8c8

commit r17-5717-ga8f38d8ca0185580d7c0944809e16e6ba5d0e8c8
Author: Pan Li <pan2...@intel.com>
Date:   Wed Oct 28 10:36:44 2026 +0800

    RISC-V: Disable RVV register overlap for vwmaccu.vx undef [PR
target/128162]

    Revert the register overlap of the widening multiply-add insn
    vwmaccu.vx undef and the related test cases.

    The insn reads the vd as the accumulator with EEW = 2 * SEW, while
    the vs1 and vs2 are read with EEW = SEW.  The section 5.2 of the
    vector spec reserves any encoding in which one vector register
    supplies source operands with two or more different EEWs.  Thus,
    the vs1 and vs2 must not overlap the vd register group, even in the
    highest-numbered part.  For example, below asm dump is reserved as
    the v3 is read with both the EEW = 32 and the EEW = 16.

      vwmaccu.vx v2,a0,v3   # LMUL = 1, SEW = 16

    This reverts commit(s):
      63fa52f94b8 RISC-V: Allow RVV register overlap for vwmaccu.vx undef
      a87ea5b3cfc RISC-V: Add test cases for vwmaccu.vx undef reg overlap
      71fe685aaad RISC-V: Add more test cases for vwmaccu.vx undef

            PR target/128162

    gcc/ChangeLog:

            * config/riscv/vector.md: Revert Wvr constraint to the
            early clobber vr.

    gcc/testsuite/ChangeLog:

            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m1.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m2.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m4.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf2.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf4.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m1.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m2.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m4.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-mf2.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m1.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m2.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m4.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf2.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf4.c: Removed.
            *
gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf8.c: Removed.
            * gcc.target/riscv/rvv/base/pr112431-59.c: Removed.

    Signed-off-by: Pan Li <pan2...@intel.com>