https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128162
--- Comment #9 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Pan Li <[email protected]>: https://gcc.gnu.org/g:f304860a0dc0c3c5b46afeea96ecf0af5ea17e0e commit r17-5720-gf304860a0dc0c3c5b46afeea96ecf0af5ea17e0e Author: Pan Li <[email protected]> Date: Wed Oct 28 10:37:58 2026 +0800 RISC-V: Disable RVV register overlap for vwmacc[u].vx [PR target/128162] Revert the register overlap of the widening multiply-add insn vwmacc[u].vx and the related test cases. The insn reads the vd as the accumulator with EEW = 2 * SEW, while the vs1 and vs2 are read with EEW = SEW. The section 5.2 of the vector spec reserves any encoding in which one vector register supplies source operands with two or more different EEWs. Thus, the vs1 and vs2 must not overlap the vd register group, even in the highest-numbered part. For example, below asm dump is reserved as the v3 is read with both the EEW = 32 and the EEW = 16. vwmacc.vx v2,a0,v3 # LMUL = 1, SEW = 16 This reverts commit(s): c69c5e7b8e0 RISC-V: Allow RVV register overlap for vwmacc[u].vx c3b9dc79868 RISC-V: Add test cases for vwmacc.vx reg overlap 24b2b8ee6bb RISC-V: Add test cases for vwmaccu.vx reg overlap db174be8290 RISC-V: Add more test cases for vwmacc[u].vx PR target/128162 gcc/ChangeLog: * config/riscv/vector.md: Revert Wvr constraint to the early clobber vr. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i16-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i16-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i16-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i16-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i16-mf4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i32-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i32-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i32-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i32-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i8-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i8-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i8-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i8-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i8-mf4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vx-i8-mf8.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf8.c: Removed. * gcc.target/riscv/rvv/base/pr112431-53.c: Removed. * gcc.target/riscv/rvv/base/pr112431-54.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h: Remove test helper macros. Signed-off-by: Pan Li <[email protected]>
