https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128162
--- Comment #12 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Pan Li <[email protected]>: https://gcc.gnu.org/g:9d6e9f2318ae218e9eb0371bfc89b8164b73473e commit r17-5749-g9d6e9f2318ae218e9eb0371bfc89b8164b73473e Author: Pan Li <[email protected]> Date: Thu Oct 29 10:16:53 2026 +0800 RISC-V: Disable RVV register overlap for vwabda[u].vv [PR target/128162] The widening absolute difference and accumulate insn vwabda[u].vv reads the vd as the accumulator with EEW = 2 * SEW, while the vs1 and vs2 are read with EEW = SEW. The section 5.2 of the vector spec reserves any encoding in which one vector register supplies source operands with two or more different EEWs. Thus, the vs1 and vs2 must not overlap the vd register group, even in the highest-numbered part. But the Wvr constraint introduced by the commit 6df026ea07b allows that, and we may have below asm dump. vwabda.vv v8,v9,v10 # LMUL = 1, SEW = 16 Disable the register overlap for vwabda[u].vv by the early clobber vr, like the other widening multiply-add insns. PR target/128162 gcc/ChangeLog: * config/riscv/vector.md: Take the early clobber vr instead of the Wvr constraint for vwabda[u].vv. Signed-off-by: Pan Li <[email protected]>
