Here is an update to the test part of this patch. I did not change the actual source code part of this, just the tests, so that is all I am including here. I removed the x86 changes that had gotten in there by accident and used relative line numbers in the warning checks instead of absolute line numbers. I also moved the warning checks to be closer to the lines where the warnings are generated.
Retested on x86 and aarch64 with no regressions. Steve Ellcey sell...@cavium.com 2018-12-21 Steve Ellcey <sell...@cavium.com> * g++.dg/gomp/declare-simd-1.C: Add aarch64 specific warning checks and assembler scans. * g++.dg/gomp/declare-simd-3.C: Ditto. * g++.dg/gomp/declare-simd-4.C: Ditto. * g++.dg/gomp/declare-simd-7.C: Ditto. * gcc.dg/gomp/declare-simd-1.c: Ditto. * gcc.dg/gomp/declare-simd-3.c: Ditto.
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C index d2659e1..f44efd5 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C @@ -14,6 +14,7 @@ int f2 (int a, int *b, int c) return a + *b + c; } +// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -89,6 +90,7 @@ namespace N1 // { dg-final { scan-assembler-times "_ZGVdN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZN2N12N23f10EPx:" 1 { target { aarch64-*-* } } } } struct A { @@ -191,6 +193,7 @@ int B<int>::f25<7> (int a, int *b, int c) return a + *b + c; } +// { dg-warning "unsupported argument type 'B<int>' for simd" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -216,6 +219,7 @@ int B<int>::f26<-1> (int a, int *b, int c) // { dg-final { scan-assembler-times "_ZGVdN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { aarch64-*-* } } } } int f27 (int x) @@ -239,6 +243,7 @@ f30 (int x) return x; } +// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-7 } // { dg-final { scan-assembler-times "_ZGVbM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -281,6 +286,7 @@ struct D int f37 (int a); int e; }; +// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-3 } void f38 (D &d) diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C index 32cdc58..3d668ff 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C @@ -21,6 +21,8 @@ int f1 (int a, int b, int c, int &d, int &e, int &f) // { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64-*-* } } } } + #pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f)) int f2 (int a, int b, int c, int &d, int &e, int &f) @@ -48,6 +50,7 @@ int f2 (int a, int b, int c, int &d, int &e, int &f) // { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64-*-* } } } } #pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f)) int f3 (const int a, const int b, const int c, const int &d, const int &e, const int &f) diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C index acf03d9..6d7e046 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C @@ -13,6 +13,8 @@ f1 (int *p, int *q, short *s) // { dg-final { scan-assembler-times "_ZGVdN8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64-*-* } } } } #pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t) int @@ -21,6 +23,7 @@ f2 (int *p, short *q, int s, int r, int &t) return *p + *q + r; } +// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -33,6 +36,7 @@ f3 (int &p, short &q, int s, int &r, int &t) return p + q + r; } +// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-7.C b/gcc/testsuite/g++.dg/gomp/declare-simd-7.C index 52e9f18..c541720 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-7.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-7.C @@ -18,6 +18,7 @@ foo1 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j, { return bar1 (a, b, c, d, e, f, g, h, i, j, k); } +// { dg-warning "unsupported argument type 'S' for simd" "" { target aarch64-*-* } .-4 } #pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \ linear (f : 2) linear (ref (g) : 1) \ @@ -28,6 +29,7 @@ foo2 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j, { return bar2 (a, b, c, d, e, f, g, h, i, j, k); } +// { dg-warning "unsupported argument type 'S' for simd" "" { target aarch64-*-* } .-4 } #pragma omp declare simd notinbranch uniform (b, c, d, e) aligned (e : 16) \ linear (f : 2) linear (ref (g) : 1) \ @@ -38,13 +40,14 @@ foo3 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j, { return bar3 (a, b, c, d, e, f, g, h, i, j, k); } +// { dg-warning "unsupported argument type 'S' for simd" "" { target aarch64-*-* } .-4 } #pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \ linear (f : 2) linear (ref (g) : 1) \ linear (val (h) : 1) linear (uval (i) : 1) \ linear (k : 4) int -foo4 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j, int k) -{ +foo4 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j, int k) { return bar4 (a, b, c, d, e, f, g, h, i, j, k); } +// { dg-warning "unsupported argument type 'S' for simd" "" { target aarch64-*-* } .-3 } diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c index b8bba1f..48e79fd 100644 --- a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c +++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c @@ -13,6 +13,7 @@ int f2 (int a, int *b, int c) return a + *b + c; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -49,6 +50,7 @@ f7 (int x) return x; } +/* { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-7 } */ /* { dg-final { scan-assembler-times "_ZGVbM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -68,6 +70,7 @@ f13 (int c; int *b; int a; int a, int *b, int c) return a + *b + c; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -86,6 +89,7 @@ f14 (a, b, c) return a + *b + c; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-7 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -102,6 +106,7 @@ f15 (int a, int *b, int c) return a + *b + c; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -139,6 +144,7 @@ int f17 (int g, long *h) /* { dg-final { scan-assembler-times "_ZGVdN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVeM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVeN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ +/* { dg-final { scan-assembler-times "f17:" 1 { target { aarch64-*-* } } } } */ #pragma omp declare simd aligned (i : sizeof (*i)) linear (j : 2 * sizeof (i[0]) + sizeof (j)) simdlen (4) int @@ -165,3 +171,4 @@ f18 (j, i) /* { dg-final { scan-assembler-times "_ZGVdN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVeM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVeN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ +/* { dg-final { scan-assembler-times "f18:" 1 { target { aarch64-*-* } } } } */ diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c index 9b8546d..e4dd074 100644 --- a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c +++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c @@ -13,6 +13,8 @@ f1 (int *p, int *q, short *s) /* { dg-final { scan-assembler-times "_ZGVdN8l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVnM4l4ln4ln6_f1:" 1 { target { aarch64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVnN4l4ln4ln6_f1:" 1 { target { aarch64-*-* } } } } */ #pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t) int @@ -21,6 +23,7 @@ f2 (int *p, short *q, int s, int r, int t) return *p + *q + r; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */