On Wed, 2019-01-16 at 08:50 +0000, Richard Sandiford wrote: > > I suggest for now we add: > > /* { dg-excess-errors "partial simd clone support" { target { aarch64*-*-* } > } } */
OK, that works. > > ...this doesn't handle explicit simdlen correctly. The vecsize_int and > vecsize_float need to be set from the user's simdlen, with num only > making a difference for the default simdlen. And there should only > be 1 size for an explicit simdlen. > > Maybe this would be more obvious if we have something like: OK, that works better, I think returning 2 instead of 1 is what was causing the ICE. I used your code to set the return value and the vecsize and everything works now. Here is a new version of the patch, it bootstraps on aarch64 and x86 and the GCC testsuite ran with no regressions on both platforms as well. Steve Ellcey sell...@marvell.com 2018-01-16 Steve Ellcey <sell...@cavium.com> * config/aarch64/aarch64.c (cgraph.h): New include. (intl.h): New include. (supported_simd_type): New function. (currently_supported_simd_type): Ditto. (aarch64_simd_clone_compute_vecsize_and_simdlen): Ditto. (aarch64_simd_clone_adjust): Ditto. (aarch64_simd_clone_usable): Ditto. (TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN): New macro. (TARGET_SIMD_CLONE_ADJUST): Ditto. (TARGET_SIMD_CLONE_USABLE): Ditto. * config/i386/i386.c (ix86_simd_clone_adjust): Add definition check. * omp-simd-clone.c (expand_simd_clones): Add targetm.simd_clone.adjust call. 2018-01-16 Steve Ellcey <sell...@cavium.com> * c-c++-common/gomp/pr60823-1.c: Add aarch64 specific warning checks and assembler scans. * c-c++-common/gomp/pr60823-3.c: Ditto. * c-c++-common/gomp/pr63328.c: Ditto. * g++.dg/gomp/declare-simd-1.C: Ditto. * g++.dg/gomp/declare-simd-3.C: Ditto. * g++.dg/gomp/declare-simd-4.C: Ditto. * g++.dg/gomp/declare-simd-7.C: Ditto. * g++.dg/gomp/pr88182.C: Ditto. * g++.dg/vect/simd-clone-7.cc: Ditto. * gcc.dg/gomp/declare-simd-1.c: Ditto. * gcc.dg/gomp/declare-simd-3.c: Ditto. * gcc.dg/gomp/pr59669-2.c: Ditto. * gcc.dg/gomp/pr87895-1.c: Ditto. * gcc.dg/gomp/pr87895-2.c: Ditto. * gcc.dg/gomp/simd-clones-2.c: Ditto. * gfortran.dg/gomp/declare-simd-2.f90: Ditto. * gfortran.dg/gomp/pr79154-1.f90: Ditto. * gfortran.dg/gomp/pr83977.f90: Ditto.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index fd60bdd..7331482 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -40,6 +40,7 @@ #include "regs.h" #include "emit-rtl.h" #include "recog.h" +#include "cgraph.h" #include "diagnostic.h" #include "insn-attr.h" #include "alias.h" @@ -71,6 +72,7 @@ #include "selftest.h" #include "selftest-rtl.h" #include "rtx-vector-builder.h" +#include "intl.h" /* This file should be included last. */ #include "target-def.h" @@ -18420,6 +18422,149 @@ aarch64_estimated_poly_value (poly_int64 val) return val.coeffs[0] + val.coeffs[1] * over_128 / 128; } + +/* Return true for types that could be supported as SIMD return or + argument types. */ + +static bool supported_simd_type (tree t) +{ + if (SCALAR_FLOAT_TYPE_P (t) || INTEGRAL_TYPE_P (t) || POINTER_TYPE_P (t)) + { + HOST_WIDE_INT s = tree_to_shwi (TYPE_SIZE_UNIT (t)); + return s == 1 || s == 2 || s == 4 || s == 8; + } + return false; +} + +/* Return true for types that currently are supported as SIMD return + or argument types. */ + +static bool currently_supported_simd_type (tree t, tree b) +{ + if (COMPLEX_FLOAT_TYPE_P (t)) + return false; + + if (TYPE_SIZE (t) != TYPE_SIZE (b)) + return false; + + return supported_simd_type (t); +} + +/* Implement TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN. */ + +static int +aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node, + struct cgraph_simd_clone *clonei, + tree base_type, int num) +{ + tree t, ret_type, arg_type; + unsigned int elt_bits, vec_bits, count; + + if (!TARGET_SIMD) + return 0; + + if (clonei->simdlen + && (clonei->simdlen < 2 + || clonei->simdlen > 1024 + || (clonei->simdlen & (clonei->simdlen - 1)) != 0)) + { + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "unsupported simdlen %d", clonei->simdlen); + return 0; + } + + ret_type = TREE_TYPE (TREE_TYPE (node->decl)); + if (TREE_CODE (ret_type) != VOID_TYPE + && !currently_supported_simd_type (ret_type, base_type)) + { + if (TYPE_SIZE (ret_type) != TYPE_SIZE (base_type)) + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "GCC does not currently support mixed size types " + "for %<simd%> functions"); + else if (supported_simd_type (ret_type)) + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "GCC does not currently support return type %qT " + "for %<simd%> functions", ret_type); + else + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "unsupported return type %qT for %<simd%> functions", + ret_type); + return 0; + } + + for (t = DECL_ARGUMENTS (node->decl); t; t = DECL_CHAIN (t)) + { + arg_type = TREE_TYPE (t); + + if (!currently_supported_simd_type (arg_type, base_type)) + { + if (TYPE_SIZE (arg_type) != TYPE_SIZE (base_type)) + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "GCC does not currently support mixed size types " + "for %<simd%> functions"); + else + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "GCC does not currently support argument type %qT " + "for %<simd%> functions", arg_type); + return 0; + } + } + + clonei->vecsize_mangle = 'n'; + clonei->mask_mode = VOIDmode; + elt_bits = GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type)); + if (clonei->simdlen == 0) + { + count = 2; + vec_bits = (num == 0 ? 64 : 128); + clonei->simdlen = vec_bits / elt_bits; + } + else + { + count = 1; + vec_bits = clonei->simdlen * elt_bits; + if (vec_bits != 64 && vec_bits != 128) + { + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "GCC does not currently support simdlen %d for type %qT", + clonei->simdlen, base_type); + return 0; + } + } + clonei->vecsize_int = vec_bits; + clonei->vecsize_float = vec_bits; + return count; +} + +/* Implement TARGET_SIMD_CLONE_ADJUST. */ + +static void +aarch64_simd_clone_adjust (struct cgraph_node *node) +{ + /* Add aarch64_vector_pcs target attribute to SIMD clones so they + use the correct ABI. */ + + tree t = TREE_TYPE (node->decl); + TYPE_ATTRIBUTES (t) = make_attribute ("aarch64_vector_pcs", "default", + TYPE_ATTRIBUTES (t)); +} + +/* Implement TARGET_SIMD_CLONE_USABLE. */ + +static int +aarch64_simd_clone_usable (struct cgraph_node *node) +{ + switch (node->simdclone->vecsize_mangle) + { + case 'n': + if (!TARGET_SIMD) + return -1; + return 0; + default: + gcc_unreachable (); + } +} + /* Target-specific selftests. */ #if CHECKING_P @@ -18913,6 +19058,16 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE aarch64_attribute_table +#undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN +#define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \ + aarch64_simd_clone_compute_vecsize_and_simdlen + +#undef TARGET_SIMD_CLONE_ADJUST +#define TARGET_SIMD_CLONE_ADJUST aarch64_simd_clone_adjust + +#undef TARGET_SIMD_CLONE_USABLE +#define TARGET_SIMD_CLONE_USABLE aarch64_simd_clone_usable + #if CHECKING_P #undef TARGET_RUN_TARGET_SELFTESTS #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index b0b7580..2f6e786 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -50649,6 +50649,11 @@ static void ix86_simd_clone_adjust (struct cgraph_node *node) { const char *str = NULL; + + /* Attributes need to be adjusted for definitions, not declarations. */ + if (!node->definition) + return; + gcc_assert (node->decl == cfun->decl); switch (node->simdclone->vecsize_mangle) { diff --git a/gcc/omp-simd-clone.c b/gcc/omp-simd-clone.c index 783118f..9b8111c 100644 --- a/gcc/omp-simd-clone.c +++ b/gcc/omp-simd-clone.c @@ -1685,6 +1685,7 @@ expand_simd_clones (struct cgraph_node *node) simd_clone_adjust (n); else { + targetm.simd_clone.adjust (n); simd_clone_adjust_return_type (n); simd_clone_adjust_argument_types (n); }
diff --git a/gcc/testsuite/c-c++-common/gomp/pr60823-1.c b/gcc/testsuite/c-c++-common/gomp/pr60823-1.c index 5f98572..d0aeb2e 100644 --- a/gcc/testsuite/c-c++-common/gomp/pr60823-1.c +++ b/gcc/testsuite/c-c++-common/gomp/pr60823-1.c @@ -17,3 +17,4 @@ foo (const double c1, const double c2) } return res; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-13 } */ diff --git a/gcc/testsuite/c-c++-common/gomp/pr60823-3.c b/gcc/testsuite/c-c++-common/gomp/pr60823-3.c index 93e9fbe..5c36286 100644 --- a/gcc/testsuite/c-c++-common/gomp/pr60823-3.c +++ b/gcc/testsuite/c-c++-common/gomp/pr60823-3.c @@ -28,5 +28,6 @@ foo (double c1, double c2) baz (*(struct S *)&c1, *(struct S *)&c2); return c1 + c2 + ((struct S *)&c1)->c[1]; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-16 } */ #endif diff --git a/gcc/testsuite/c-c++-common/gomp/pr63328.c b/gcc/testsuite/c-c++-common/gomp/pr63328.c index 3958abe..54eface 100644 --- a/gcc/testsuite/c-c++-common/gomp/pr63328.c +++ b/gcc/testsuite/c-c++-common/gomp/pr63328.c @@ -3,3 +3,5 @@ /* { dg-options "-O2 -fopenmp-simd -fno-strict-aliasing -fcompare-debug" } */ #include "pr60823-3.c" +/* { dg-excess-errors "partial simd clone support" { target { aarch64*-*-* } } } */ + diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C index d2659e1..cc17c9c 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C @@ -14,6 +14,7 @@ int f2 (int a, int *b, int c) return a + *b + c; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -89,6 +90,8 @@ namespace N1 // { dg-final { scan-assembler-times "_ZGVdN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnM2va16__ZN2N12N23f10EPx:" 1 { target { aarch64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnN2va16__ZN2N12N23f10EPx:" 1 { target { aarch64-*-* } } } } struct A { @@ -191,6 +194,7 @@ int B<int>::f25<7> (int a, int *b, int c) return a + *b + c; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -208,6 +212,7 @@ int B<int>::f26<-1> (int a, int *b, int c) return a + *b + c; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -239,6 +244,7 @@ f30 (int x) return x; } +// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-7 } // { dg-final { scan-assembler-times "_ZGVbM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -281,6 +287,7 @@ struct D int f37 (int a); int e; }; +// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-3 } void f38 (D &d) diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C index 32cdc58..0706c79 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C @@ -13,6 +13,7 @@ int f1 (int a, int b, int c, int &d, int &e, int &f) return a + b + c + d + e + f; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-11 } // { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -21,6 +22,7 @@ int f1 (int a, int b, int c, int &d, int &e, int &f) // { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } + #pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f)) int f2 (int a, int b, int c, int &d, int &e, int &f) @@ -40,6 +42,7 @@ int f2 (int a, int b, int c, int &d, int &e, int &f) return a + b + c + d + e + f; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-17 } // { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -55,6 +58,7 @@ int f3 (const int a, const int b, const int c, const int &d, const int &e, const return a + b + c + d + e + f; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -76,6 +80,7 @@ int f4 (const int a, const int b, const int c, const int &d, const int &e, const return a + b + c + d + e + f; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-11 } // { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C index acf03d9..1289f48 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C @@ -5,6 +5,7 @@ f1 (int *p, int *q, short *s) return *p + *q + *s; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -21,6 +22,7 @@ f2 (int *p, short *q, int s, int r, int &t) return *p + *q + r; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -33,6 +35,7 @@ f3 (int &p, short &q, int s, int &r, int &t) return p + q + r; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-7.C b/gcc/testsuite/g++.dg/gomp/declare-simd-7.C index 52e9f18..1614db5 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-7.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-7.C @@ -18,6 +18,7 @@ foo1 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j, { return bar1 (a, b, c, d, e, f, g, h, i, j, k); } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 } #pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \ linear (f : 2) linear (ref (g) : 1) \ @@ -28,6 +29,7 @@ foo2 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j, { return bar2 (a, b, c, d, e, f, g, h, i, j, k); } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 } #pragma omp declare simd notinbranch uniform (b, c, d, e) aligned (e : 16) \ linear (f : 2) linear (ref (g) : 1) \ @@ -38,6 +40,7 @@ foo3 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j, { return bar3 (a, b, c, d, e, f, g, h, i, j, k); } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 } #pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \ linear (f : 2) linear (ref (g) : 1) \ @@ -48,3 +51,4 @@ foo4 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j, { return bar4 (a, b, c, d, e, f, g, h, i, j, k); } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 } diff --git a/gcc/testsuite/g++.dg/gomp/pr88182.C b/gcc/testsuite/g++.dg/gomp/pr88182.C index 6eeeed9..c783edc 100644 --- a/gcc/testsuite/g++.dg/gomp/pr88182.C +++ b/gcc/testsuite/g++.dg/gomp/pr88182.C @@ -18,6 +18,7 @@ foo (double c1, double c2) } return res; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-15 } __attribute__((noinline, noclone)) void bar (double *x, double *y) diff --git a/gcc/testsuite/g++.dg/vect/simd-clone-7.cc b/gcc/testsuite/g++.dg/vect/simd-clone-7.cc index fd5751b..c2a63cd 100644 --- a/gcc/testsuite/g++.dg/vect/simd-clone-7.cc +++ b/gcc/testsuite/g++.dg/vect/simd-clone-7.cc @@ -8,3 +8,4 @@ bar (float x, float *y, int) { return y[0] + y[1] * x; } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 } diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c index b8bba1f..003b054 100644 --- a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c +++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c @@ -13,6 +13,7 @@ int f2 (int a, int *b, int c) return a + *b + c; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -49,6 +50,7 @@ f7 (int x) return x; } +/* { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-7 } */ /* { dg-final { scan-assembler-times "_ZGVbM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -68,6 +70,7 @@ f13 (int c; int *b; int a; int a, int *b, int c) return a + *b + c; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -86,6 +89,7 @@ f14 (a, b, c) return a + *b + c; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-7 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -102,6 +106,7 @@ f15 (int a, int *b, int c) return a + *b + c; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -123,6 +128,7 @@ int f17 (int g, long *h) return g + h[0]; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ @@ -149,6 +155,7 @@ f18 (j, i) return j + i[0]; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-7 } */ /* { dg-final { scan-assembler-times "_ZGVbM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c index 9b8546d..66dc740 100644 --- a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c +++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c @@ -5,6 +5,7 @@ f1 (int *p, int *q, short *s) return *p + *q + *s; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -21,6 +22,7 @@ f2 (int *p, short *q, int s, int r, int t) return *p + *q + r; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ diff --git a/gcc/testsuite/gcc.dg/gomp/pr59669-2.c b/gcc/testsuite/gcc.dg/gomp/pr59669-2.c index f6aad89..46294db 100644 --- a/gcc/testsuite/gcc.dg/gomp/pr59669-2.c +++ b/gcc/testsuite/gcc.dg/gomp/pr59669-2.c @@ -7,3 +7,4 @@ void bar (int *a) { } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-3 } */ diff --git a/gcc/testsuite/gcc.dg/gomp/pr87895-1.c b/gcc/testsuite/gcc.dg/gomp/pr87895-1.c index 22f5c69..7f5397b 100644 --- a/gcc/testsuite/gcc.dg/gomp/pr87895-1.c +++ b/gcc/testsuite/gcc.dg/gomp/pr87895-1.c @@ -17,3 +17,4 @@ bar (int *x, int y) if ((y == 0) ? (*x = 0) : *x) return 0; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } */ diff --git a/gcc/testsuite/gcc.dg/gomp/pr87895-2.c b/gcc/testsuite/gcc.dg/gomp/pr87895-2.c index 3d27715..26827ac 100644 --- a/gcc/testsuite/gcc.dg/gomp/pr87895-2.c +++ b/gcc/testsuite/gcc.dg/gomp/pr87895-2.c @@ -3,3 +3,4 @@ /* { dg-additional-options "-O1" } */ #include "pr87895-1.c" +/* { dg-excess-errors "partial simd clone support" { target { aarch64*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c b/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c index df7f631..3201c96 100644 --- a/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c +++ b/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c @@ -6,6 +6,7 @@ int addit(int a, int b, int *c) { return a + b; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 } */ #pragma omp declare simd uniform(a) aligned(a:32) linear(k:1) notinbranch float setArray(float *a, float x, int k) @@ -14,6 +15,7 @@ float setArray(float *a, float x, int k) return a[k]; } +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-6 } */ /* { dg-final { scan-tree-dump "_ZGVbN4ua32vl_setArray" "optimized" { target i?86-*-* x86_64-*-* } } } */ /* { dg-final { scan-tree-dump "_ZGVbN4vvva32_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */ /* { dg-final { scan-tree-dump "_ZGVbM4vl66u_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */ diff --git a/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90 b/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90 index 8f76774..fd4e119 100644 --- a/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90 +++ b/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90 @@ -1,6 +1,6 @@ ! { dg-do compile } -function f1 (a, b, c, d, e, f) +function f1 (a, b, c, d, e, f) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" } integer, value :: a, b, c integer :: d, e, f, f1 !$omp declare simd (f1) uniform(b) linear(c, d) linear(uval(e)) linear(ref(f)) @@ -12,7 +12,7 @@ function f1 (a, b, c, d, e, f) f = f + 1 f1 = a + b + c + d + e + f end function f1 -integer function f2 (a, b) +integer function f2 (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" } integer :: a, b !$omp declare simd uniform(b) linear(ref(a):b) a = a + 1 diff --git a/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90 b/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90 index 6c86ded..953dcad 100644 --- a/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90 +++ b/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90 @@ -1,7 +1,7 @@ ! PR fortran/79154 ! { dg-do compile } -pure real function foo (a, b) +pure real function foo (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" } !$omp declare simd(foo) ! { dg-bogus "may not appear in PURE or ELEMENTAL" } real, intent(in) :: a, b foo = a + b @@ -20,7 +20,7 @@ pure real function baz (a, b) real, intent(in) :: a, b baz = a + b end function baz -elemental real function fooe (a, b) +elemental real function fooe (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" } !$omp declare simd(fooe) ! { dg-bogus "may not appear in PURE or ELEMENTAL" } real, intent(in) :: a, b fooe = a + b diff --git a/gcc/testsuite/gfortran.dg/gomp/pr83977.f90 b/gcc/testsuite/gfortran.dg/gomp/pr83977.f90 index b8ad1a7..6dfdbc3 100644 --- a/gcc/testsuite/gfortran.dg/gomp/pr83977.f90 +++ b/gcc/testsuite/gfortran.dg/gomp/pr83977.f90 @@ -1,7 +1,7 @@ ! PR middle-end/83977 ! { dg-do compile } -integer function foo (a, b) +integer function foo (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" } integer :: a, b !$omp declare simd uniform(b) linear(ref(a):b) a = a + 1