On Fri, 2019-01-11 at 14:45 +0000, Richard Sandiford wrote: > > > + > > +/* Return true for types that could be supported as SIMD return or > > + argument types. */ > > + > > +static bool supported_simd_type (tree t) > > +{ > > + return (FLOAT_TYPE_P (t) || INTEGRAL_TYPE_P (t)); > > We should also check that the size is 1, 2, 4 or 8 bytes.
I fixed this, I also allow for POINTER_P types which allowed me to not do the POINTER_P check below which you asked about and which I now think was a mistake (more comments below). > > > > + wmsg = G_("unsupported return type return type %qT for simd"); > > Typo: doubled "return type". Fixed. > > Maybe s/for simd/for %<simd%> functions/ in both messages. > Since that will blow the line limit... > > > + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, wmsg, > > ret_type); > > + return 0; > > + } > > ...it's probably worth just calling warning_at in each arm of the > "if". > We'll then get proper format checking in bootstraps. I made this change. > > + for (t = DECL_ARGUMENTS (node->decl); t; t = DECL_CHAIN (t)) > > + { > > + arg_type = TREE_TYPE (t); > > + if (POINTER_TYPE_P (arg_type)) > > + arg_type = TREE_TYPE (arg_type); > > + if (!currently_supported_simd_type (arg_type)) > > + { > > + if (supported_simd_type (arg_type)) > > + wmsg = G_("GCC does not currently support argument type %qT > > " > > + "for simd"); > > + else > > + wmsg = G_("unsupported argument type %qT for simd"); > > + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, wmsg, > > arg_type); > > + return 0; > > + } > > + } > > The ABI supports all argument types, so this should only check > current_supported_simd_type and should always use the "GCC does > not..." > message. Done. > Could you explain why the POINTER_TYPE_P handling is correct? > Think it's worth a comment. Dropping it is also fine if that's > easier. I now think this was a mistake but after removing it I had to allow for POINTER_P type in supported_simd_type to get the regression tests to pass. I think the current code is the correct behavour and more closely matches x86 in terms of what is and is not vectorized. > > + if (clonei->simdlen == 0) > > + { > > + if (SCALAR_INT_MODE_P (TYPE_MODE (base_type))) > > + clonei->simdlen = clonei->vecsize_int; > > + else > > + clonei->simdlen = clonei->vecsize_float; > > + clonei->simdlen /= GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type)); > > + return 1; > > + } > > I should have noticed this last time, but base_type is the CDT in the > Intel ABI. That isn't always right for the AArch64 ABI. > > I think for now currently_supported_simd_type should take base_type > as a second parameter and check that the given type has the same > size. I have not changed this, I am not quite sure what you mean. What is CDT? Clone data type? Are you saying I should use node->decl->type instead of base_type? > > > + /* Restrict ourselves to vectors that fit in a single > > register */ > > + > > + gcc_assert (tree_fits_shwi_p (TYPE_SIZE (base_type))); > > + vsize = clonei->simdlen * tree_to_shwi (TYPE_SIZE (base_type)); > > + if (vsize > 128) > > + { > > + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, > > + "GCC does not currently support simdlen %d for > > type %qT", > > + clonei->simdlen, base_type); > > + return 0; > > + } > > nit: block contents indented too far. Fixed. > > + return 0; > > +} > > Doesn't this mean that we always silently fail for an explicit and > correct simdlen? If so, that suggests we might not have enough > testsuite coverage :-) Well, we were failing here and some tests were failing but then I 'fixed' the tests in my last patch to pass instead of fixing this bug. I have now changed it to 'return 1' and re-fixed the tests that I incorrectly fixed last time. So at least it wasn't a silent fail (until I silenced it). Here is the latest patch, any help you can give me on the base_type issue would be appreciated. 2018-01-11 Steve Ellcey <sell...@cavium.com> * config/aarch64/aarch64.c (cgraph.h): New include. (intl.h): New include. (supported_simd_type): New function. (currently_supported_simd_type): Ditto. (aarch64_simd_clone_compute_vecsize_and_simdlen): Ditto. (aarch64_simd_clone_adjust): Ditto. (aarch64_simd_clone_usable): Ditto. (TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN): New macro. (TARGET_SIMD_CLONE_ADJUST): Ditto. (TARGET_SIMD_CLONE_USABLE): Ditto. * config/i386/i386.c (ix86_simd_clone_adjust): Add definition check. * omp-simd-clone.c (expand_simd_clones): Add targetm.simd_clone.adjust call. 2018-01-11 Steve Ellcey <sell...@cavium.com> * g++.dg/gomp/declare-simd-1.C: Add aarch64 specific warning checks and assembler scans. * g++.dg/gomp/declare-simd-3.C: Ditto. * g++.dg/gomp/declare-simd-4.C: Ditto. * gcc.dg/gomp/declare-simd-1.c: Ditto. * gcc.dg/gomp/declare-simd-3.c: Ditto.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index fd60bdd..360adea 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -40,6 +40,7 @@ #include "regs.h" #include "emit-rtl.h" #include "recog.h" +#include "cgraph.h" #include "diagnostic.h" #include "insn-attr.h" #include "alias.h" @@ -71,6 +72,7 @@ #include "selftest.h" #include "selftest-rtl.h" #include "rtx-vector-builder.h" +#include "intl.h" /* This file should be included last. */ #include "target-def.h" @@ -18420,6 +18422,140 @@ aarch64_estimated_poly_value (poly_int64 val) return val.coeffs[0] + val.coeffs[1] * over_128 / 128; } + +/* Return true for types that could be supported as SIMD return or + argument types. */ + +static bool supported_simd_type (tree t) +{ + HOST_WIDE_INT s; + gcc_assert (tree_fits_shwi_p (TYPE_SIZE_UNIT (t))); + s = tree_to_shwi (TYPE_SIZE_UNIT (t)); + return ((FLOAT_TYPE_P (t) || INTEGRAL_TYPE_P (t) || POINTER_TYPE_P (t)) + && (s == 1 || s == 2 || s == 4 || s == 8)); +} + +/* Return true for types that currently are supported as SIMD return + or argument types. */ + +static bool currently_supported_simd_type (tree t) +{ + if (COMPLEX_FLOAT_TYPE_P (t)) + return false; + + return supported_simd_type (t); +} + +/* Implement TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN. */ + +static int +aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node, + struct cgraph_simd_clone *clonei, + tree base_type, + int num ATTRIBUTE_UNUSED) +{ + int vsize; + tree t, ret_type, arg_type; + + if (!TARGET_SIMD) + return 0; + + if (clonei->simdlen + && (clonei->simdlen < 2 + || clonei->simdlen > 1024 + || (clonei->simdlen & (clonei->simdlen - 1)) != 0)) + { + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "unsupported simdlen %d", clonei->simdlen); + return 0; + } + + ret_type = TREE_TYPE (TREE_TYPE (node->decl)); + if (TREE_CODE (ret_type) != VOID_TYPE + && !currently_supported_simd_type (ret_type)) + { + if (supported_simd_type (ret_type)) + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "GCC does not currently support return type %qT " + "for %<simd%> functions", ret_type); + else + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "unsupported return type %qT for %<simd%> functions", + ret_type); + return 0; + } + + for (t = DECL_ARGUMENTS (node->decl); t; t = DECL_CHAIN (t)) + { + arg_type = TREE_TYPE (t); + + if (!currently_supported_simd_type (arg_type)) + { + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "GCC does not currently support argument type %qT " + "for %<simd%> functions", arg_type); + return 0; + } + } + + clonei->vecsize_mangle = 'n'; + clonei->mask_mode = VOIDmode; + clonei->vecsize_int = 128; + clonei->vecsize_float = 128; + + if (clonei->simdlen == 0) + { + if (SCALAR_INT_MODE_P (TYPE_MODE (base_type))) + clonei->simdlen = clonei->vecsize_int; + else + clonei->simdlen = clonei->vecsize_float; + clonei->simdlen /= GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type)); + return 1; + } + + /* Restrict ourselves to vectors that fit in a single register */ + + gcc_assert (tree_fits_shwi_p (TYPE_SIZE (base_type))); + vsize = clonei->simdlen * tree_to_shwi (TYPE_SIZE (base_type)); + if (vsize > 128) + { + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "GCC does not currently support simdlen %d for type %qT", + clonei->simdlen, base_type); + return 0; + } + return 1; +} + +/* Implement TARGET_SIMD_CLONE_ADJUST. */ + +static void +aarch64_simd_clone_adjust (struct cgraph_node *node) +{ + /* Add aarch64_vector_pcs target attribute to SIMD clones so they + use the correct ABI. */ + + tree t = TREE_TYPE (node->decl); + TYPE_ATTRIBUTES (t) = + make_attribute ("aarch64_vector_pcs", "default", TYPE_ATTRIBUTES (t)); +} + +/* Implement TARGET_SIMD_CLONE_USABLE. */ + +static int +aarch64_simd_clone_usable (struct cgraph_node *node) +{ + switch (node->simdclone->vecsize_mangle) + { + case 'n': + if (!TARGET_SIMD) + return -1; + return 0; + default: + gcc_unreachable (); + } +} + /* Target-specific selftests. */ #if CHECKING_P @@ -18913,6 +19049,16 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE aarch64_attribute_table +#undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN +#define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \ + aarch64_simd_clone_compute_vecsize_and_simdlen + +#undef TARGET_SIMD_CLONE_ADJUST +#define TARGET_SIMD_CLONE_ADJUST aarch64_simd_clone_adjust + +#undef TARGET_SIMD_CLONE_USABLE +#define TARGET_SIMD_CLONE_USABLE aarch64_simd_clone_usable + #if CHECKING_P #undef TARGET_RUN_TARGET_SELFTESTS #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 1bb535a..82e0f90 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -50648,6 +50648,11 @@ static void ix86_simd_clone_adjust (struct cgraph_node *node) { const char *str = NULL; + + /* Attributes need to be adjusted for definitions, not declarations. */ + if (!node->definition) + return; + gcc_assert (node->decl == cfun->decl); switch (node->simdclone->vecsize_mangle) { diff --git a/gcc/omp-simd-clone.c b/gcc/omp-simd-clone.c index 783118f..9b8111c 100644 --- a/gcc/omp-simd-clone.c +++ b/gcc/omp-simd-clone.c @@ -1685,6 +1685,7 @@ expand_simd_clones (struct cgraph_node *node) simd_clone_adjust (n); else { + targetm.simd_clone.adjust (n); simd_clone_adjust_return_type (n); simd_clone_adjust_argument_types (n); }
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C index d2659e1..c147978 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C @@ -14,6 +14,7 @@ int f2 (int a, int *b, int c) return a + *b + c; } +// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -89,6 +90,8 @@ namespace N1 // { dg-final { scan-assembler-times "_ZGVdN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnM2va16__ZN2N12N23f10EPx:" 1 { target { aarch64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnN2va16__ZN2N12N23f10EPx:" 1 { target { aarch64-*-* } } } } struct A { @@ -191,6 +194,7 @@ int B<int>::f25<7> (int a, int *b, int c) return a + *b + c; } +// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -216,6 +220,8 @@ int B<int>::f26<-1> (int a, int *b, int c) // { dg-final { scan-assembler-times "_ZGVdN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { aarch64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { aarch64-*-* } } } } int f27 (int x) @@ -239,6 +245,7 @@ f30 (int x) return x; } +// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-7 } // { dg-final { scan-assembler-times "_ZGVbM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVbN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -281,6 +288,7 @@ struct D int f37 (int a); int e; }; +// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-3 } void f38 (D &d) diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C index 32cdc58..3d668ff 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C @@ -21,6 +21,8 @@ int f1 (int a, int b, int c, int &d, int &e, int &f) // { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64-*-* } } } } + #pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f)) int f2 (int a, int b, int c, int &d, int &e, int &f) @@ -48,6 +50,7 @@ int f2 (int a, int b, int c, int &d, int &e, int &f) // { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64-*-* } } } } #pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f)) int f3 (const int a, const int b, const int c, const int &d, const int &e, const int &f) diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C index acf03d9..6d7e046 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C @@ -13,6 +13,8 @@ f1 (int *p, int *q, short *s) // { dg-final { scan-assembler-times "_ZGVdN8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVnN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64-*-* } } } } #pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t) int @@ -21,6 +23,7 @@ f2 (int *p, short *q, int s, int r, int &t) return *p + *q + r; } +// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } @@ -33,6 +36,7 @@ f3 (int &p, short &q, int s, int &r, int &t) return p + q + r; } +// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } // { dg-final { scan-assembler-times "_ZGVbN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c index b8bba1f..ec53ebe 100644 --- a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c +++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c @@ -13,6 +13,7 @@ int f2 (int a, int *b, int c) return a + *b + c; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -49,6 +50,7 @@ f7 (int x) return x; } +/* { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-7 } */ /* { dg-final { scan-assembler-times "_ZGVbM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -68,6 +70,7 @@ f13 (int c; int *b; int a; int a, int *b, int c) return a + *b + c; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -86,6 +89,7 @@ f14 (a, b, c) return a + *b + c; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-7 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -102,6 +106,7 @@ f15 (int a, int *b, int c) return a + *b + c; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ @@ -139,6 +144,8 @@ int f17 (int g, long *h) /* { dg-final { scan-assembler-times "_ZGVdN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVeM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVeN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVnM4l20va8_f17:" 1 { target { aarch64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVnN4l20va8_f17:" 1 { target { aarch64-*-* } } } } */ #pragma omp declare simd aligned (i : sizeof (*i)) linear (j : 2 * sizeof (i[0]) + sizeof (j)) simdlen (4) int @@ -165,3 +172,5 @@ f18 (j, i) /* { dg-final { scan-assembler-times "_ZGVdN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVeM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVeN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVnM4l20va8_f18:" 1 { target { aarch64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVnN4l20va8_f18:" 1 { target { aarch64-*-* } } } } */ diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c index 9b8546d..e4dd074 100644 --- a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c +++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c @@ -13,6 +13,8 @@ f1 (int *p, int *q, short *s) /* { dg-final { scan-assembler-times "_ZGVdN8l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVnM4l4ln4ln6_f1:" 1 { target { aarch64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVnN4l4ln4ln6_f1:" 1 { target { aarch64-*-* } } } } */ #pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t) int @@ -21,6 +23,7 @@ f2 (int *p, short *q, int s, int r, int t) return *p + *q + r; } +/* { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64-*-* } .-5 } */ /* { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */