Hi,
Segher Boessenkool <seg...@kernel.crashing.org> writes:
> Hi!
>
> On Fri, Dec 23, 2022 at 08:36:36PM +0800, Jiufu Guo wrote:
>> It seems some limitations there. e.g. 1. "subreg:DF on DI register"
>> may not work well on pseudo,
>
> It is perfectly normal:
> A hard register may be accessed in various modes throughout one
> function, but each pseudo register is given a natural mode
> and is accessed only in that mode. When it is necessary to describe
> an access to a pseudo register using a nonnatural mode, a @code{subreg}
> expression is used.
>
> and:
> @code{subreg} expressions are used to refer to a register in a machine
> mode other than its natural one, or to refer to one register of
> a multi-part @code{reg} that actually refers to several registers.
>
> Each pseudo register has a natural mode. If it is necessary to
> operate on it in a different mode, the register must be
> enclosed in a @code{subreg}.
>
> and we even have:
> @item hard registers
> It is seldom necessary to wrap hard registers in @code{subreg}s; such
> registers would normally reduce to a single @code{reg} rtx. This use of
> @code{subreg}s is discouraged and may not be supported in the future.
>
Thanks so much for detailed explaination!
>> and 2. to convert high-part:DI to SF,
>> a "shift/rotate" is needed, and then we need to "emit shift insn"
>> in cse. I may need to update this patch.
>
> Hrm. The machine insns to do this is just mtvsrd;xscvspdpn, but for
> converting the lowpart it is mtvsrws;xscvspdpn (this needs p9 or
> later). We should arrive at those patterns, and we should try to not
> go via the more expensive formulations with shifts, which don't describe
> the hardware well, and which overestimate the cost of it.
Yes, understant!
>
> None of this belongs in generic code at all imo. At expand time it
> should be expanded to something that works and can be optimised well,
> so not anything with :BLK (which has to be put in memory, something with
> unbounded size cannot be put in registers), not anything specifically
> tailored to any cpu, something nice and regular. Using a subreg (of a
> pseudo!) is the standard way of writing a bitcast.
>
> So generic code would do a (subreg:SF (reg:SI) 0) to express a 32-bit
> integer bitcast to an IEEE SP number, and our machine description should
> make it work nicely.
Right! So, I'm thinking a way: in generic code, we may generated
"shift+(subreg:SF (reg:SI) 0)"; and at somewhere (maybe in combiner),
using "mtvsr.." to replace the "shift+subreg".
BR,
Jeff (Jiufu)
>
>
> Segher
