Sorry for send this mail. I enter the wrong command line. -----Original Message----- From: Gcc-patches <gcc-patches-bounces+lin1.hu=intel....@gcc.gnu.org> On Behalf Of Segher Boessenkool Sent: Tuesday, January 3, 2023 5:00 PM To: Andrew Pinski <pins...@gmail.com> Cc: Jiufu Guo <guoji...@linux.ibm.com>; Jiufu Guo via Gcc-patches <gcc-patches@gcc.gnu.org>; Richard Biener <richard.guent...@gmail.com>; Richard Biener <rguent...@suse.de>; dje....@gmail.com; li...@gcc.gnu.org; jeffreya...@gmail.com Subject: Re: [PATCH] loading float member of parameter stored via int registers
Hi! On Fri, Dec 30, 2022 at 12:30:04AM -0800, Andrew Pinski wrote: > On Thu, Dec 29, 2022 at 11:45 PM Segher Boessenkool > <seg...@kernel.crashing.org> wrote: > > Ah! This simply shows rs6000_modes_tieable_p is decidedly non-optimal: > > it does not allow tying a scalar float to anything else. No such > > thing is required, or good apparently. I wonder why we have such > > restrictions at all in rs6000; is it just unfortunate history, was > > it good at one point in time? > > The documentation for TARGET_MODES_TIEABLE_P says the following: > If TARGET_HARD_REGNO_MODE_OK (r, mode1) and TARGET_HARD_REGNO_MODE_OK > (r, mode2) are always the same for any r, then TARGET_MODES_TIEABLE_P > (mode1, mode2) should be true. If they differ for any r, you should > define this hook to return false unless some other mechanism ensures > the accessibility of the value in a narrower mode. > > even though rs6000_hard_regno_mode_ok_uncached's comment has the following: > /* The float registers (except for VSX vector modes) can only hold floating > modes and DImode. */ That comment is incorrect. See fctiw for example, which defines only the SImode part of the result (the other bits are undefined). > TARGET_P8_VECTOR and TARGET_P9_VECTOR has special cased different modes now: > if (TARGET_P8_VECTOR && (mode == SImode)) > return 1; > > if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode)) > return 1; > Which I suspect that means rs6000_modes_tieable_p should return true > for SImode and SFmode if TARGET_P8_VECTOR is true. Likewise for > TARGET_P9_VECTOR and SFmode and QImode/HImode too. It means that older CPUs do not have as many instructions to do scalar integer operations in vector registers, making it (almost) always a losing proposition to put scalar integers there. On newer CPUs it is not quite as bad, there is a full(er) complement of instructions to do such things in vector regs, just a bit slower than on GPRs. But yeah we might need to fix hard_regno_mode_ok if we change tieable. Segher
