> On 18 Aug 2017, at 11:13 AM, Michael Clark <[email protected]> wrote:
>
> So it is a bug on arm too? and can be done with one sbfiz instruction?
> (assuming I’m understand sbfiz from my first reading) e.g.
>
> sbfiz w0, w0, 0, 2
> ret
Getting my 3’s and 5’s swapped. Confused by gcc.
sbfiz w0, w0, 0, 4
>> Which is:
>> (insn 7 6 8 2 (set (reg:SI 80)
>> (sign_extend:SI (ashift:QI (reg:QI 0 x0 [ x+3 ])
>> (const_int 3 [0x3])))) t.cc:5 557 {*extendsi_ashlqi}
>> (expr_list:REG_DEAD (reg:SI 0 x0 [ x ])
>> (nil)))
>>
>> (insn 14 9 17 2 (set (reg/i:SI 0 x0)
>> (ashiftrt:SI (reg:SI 80)
>> (const_int 3 [0x3]))) t.cc:10 530 {*aarch64_ashr_sisd_or_int_si3}
>> (expr_list:REG_DEAD (reg:SI 80)
>> (nil)))
>>
>> What I suspect is we get a QImode register in there and that is what
>> is happening to both x86 and riscv.
>
