On Fri, 2017-08-18 at 10:29 +1200, Michael Clark wrote: > > This one is quite interesting: > > - https://cx.rv8.io/g/WXWMTG > > It’s another target independent bug. x86 is using some LEA followed > by SAR trick with a 3 bit shift. Surely SHL 27, SAR 27 would suffice. > In any case RISC-V seems like a nice target to try to fix this > codegen for, as its less risk than attempting a fix in x86 ;-) > > - https://github.com/riscv/riscv-gcc/issues/89 > > code: > > template <typename T, unsigned B> > inline T signextend(const T x) > { > struct {T x:B;} s; > return s.x = x; > } > > int sx5(int x) { > return signextend<signed int,5>(x); > } > > riscv asm: > > sx5(int): > slliw a0,a0,3 > slliw a0,a0,24 > sraiw a0,a0,24 > sraiw a0,a0,3 > ret > > hand coded riscv asm > > sx5(int): > slliw a0,a0,27 > sraiw a0,a0,27 > ret >
Maybe related ... https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67644 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=50521 Cheers, Oleg
