On Fri, Aug 18, 2017 at 10:29:04AM +1200, Michael Clark wrote: > Sorry I had to send again as my Apple mailer is munging emails. I’ve disabled > RTF. > > > This one is quite interesting: > > - https://cx.rv8.io/g/WXWMTG > > It’s another target independent bug. x86 is using some LEA followed by SAR > trick with a 3 bit shift. Surely SHL 27, SAR 27 would suffice. In any case > RISC-V seems like a nice target to try to fix this codegen for, as its less > risk than attempting a fix in x86 ;-) > > - https://github.com/riscv/riscv-gcc/issues/89 > > code: > > template <typename T, unsigned B> > inline T signextend(const T x) > { > struct {T x:B;} s; > return s.x = x; > } > > int sx5(int x) { > return signextend<signed int,5>(x); > } > > riscv asm: > > sx5(int): > slliw a0,a0,3 > slliw a0,a0,24 > sraiw a0,a0,24 > sraiw a0,a0,3 > ret > > hand coded riscv asm > > sx5(int): > slliw a0,a0,27 > sraiw a0,a0,27 > ret > > x86 asm: > > sx5(int): > lea eax, [0+rdi*8] > sar al, 3 > movsx eax, al > ret > > hand coded x86 asm (no worse because the sar depends on the lea) > > sx5(int): > shl edi, 27 > sar edi, 27 > movsx eax, dl
Huh? dl is not a subreg of edi! s/edi/edx/ and it may work. dil can also be used, but only on 64 bit. Gabriel