I tried the -y switch. I have a directory ../modules with files like ver_7400 containing module ver_7400(O,A,B); ... endmodule
My source file contains ver_7400 U8 (...) iverilog -y ../modules source.vl complains source.vl:54: error: Unknown module type: ver_7400 ... I tried iverilog -y /usr/home/tomdean/cad/verilog/modules source.vl same result. If I do iverilog source.vl ../modules/* it seems to find all the modules. There are some modules defined that are not needed in source.vl. The compiler seems to not put these not needed definitions in the output. # iverilog -V Icarus Verilog version 0.8 ($Name: v0_8_1 $) Copyright 1998-2003 Stephen Williams ... What am I doing wrong? tomdean _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user