it looks like iverilog does not accept +define+.v from the command line,
but as it is the default, not a big issue.
[EMAIL PROTECTED] ~]$ iverilog -y lib test.v && ./a.out
out is 0 at 0
out is 1 at 25
out is 2 at 35
out is 3 at 45
<snip>
perhaps your module file is not called module_name.v ??
john
User Tomdean wrote:
I tried the -y switch.
I have a directory ../modules with files like ver_7400 containing
module ver_7400(O,A,B);
test.v :
module test ();
reg clk, rst;
initial
begin clk = 1'b0;
forever #5 clk = !clk;
end
initial
begin
rst=1'b1;
#20 rst = 0;
#100 $finish;
end
wire [5:0] out;
counter count0 (.clk(clk), .rst(rst), .out(out));
always @ (out)
$display("out is %0d at %0t", out, $time);
endmodule // test
lib/counter.v :
module counter (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, rst
);
input clk;
input rst;
output out;
reg [5:0] out;
always @ (posedge clk or posedge rst)
if (rst)
out <= 0;
else
out <= out + 1'b1;
endmodule // counter
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