> -------- Original Message -------- > Subject: Re: gEDA-user: verilog -> gschem > From: Steven Michalske <smichal...@gmail.com> > Date: Fri, July 08, 2011 1:46 pm > To: gEDA user mailing list <geda-user@moria.seul.org > > Will the gentlest backend for verilog accept symbols with the source > attribute set, like hierarchy symbols, but > making them point to Verilog > source not a sch source? > > Steve
I could see that being useful, doesn't solve my issue as I need to have the final netlist in bdnet format but the ability to synthesize a block into verilog and reference it in a schematic...actually you can basically do that. Set the 'device' attribute of the symbol to the name of the .v file and make sure the file can be found by icarus or that the device exists in a library file. The verilog netlister (at least when using the geda_hier_tools.bsh script I found in the mailing list archives) will produce a nice verilog file and any symbol with a 'device' attribute is assumed to have a verilog source associated with it as I understand it. I'm doing a standard cell design so I got the verilog library from the fab, I created symbols for the library parts and set 'device' to the cell name as it exists in the library file, 'pinnumber's are set to the port names of each device and it netlists properly (netlist by name, not port order). In icarus I include the library file and UDP file with the verilog netlist from geda_hier_tools.bsh and it runs great. _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user