Hi, (Sorry for the top post)
No autorouter is needed... Just place the generated symbols on a grid, so they don't touch, and add wire stubs to each pin. Each wire should have a netname attribute attached. The netlister will connect all similarly named nets together. Any reason you can't just instantiate the verilog from the external sources directly? Or do you desire a flattened netlist for some reason? Thanks, Mike -----Original Message----- From: Ouabache Designworks <z3qmt...@gmail.com> Sender: geda-user-boun...@moria.seul.org Date: Fri, 8 Jul 2011 09:43:02 To: <geda-user@moria.seul.org> Reply-To: gEDA user mailing list <geda-user@moria.seul.org> Subject: Re: gEDA-user: verilog -> gschem _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
