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Hi Sophiane, Thanks for the contribution. It looks like some of the patch doesn't apply cleanly in reviewboard. Did you use the hg postreview extension? It may also help to use the "-o" option on the extension. Cheers! - Jason Lowe-Power On June 16, 2016, 1:37 p.m., Sophiane SENNI wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3502/ > ----------------------------------------------------------- > > (Updated June 16, 2016, 1:37 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10875:b498767cb7d8 > --------------------------- > cache: Split the hit latency into tag lookup latency and RAM access latency > > If the cache access mode is parallel ("sequential_access" parameter set to > "False"), tags and RAMs are accessed in parallel. Therefore, the hit latency > is the maximum latency between tag lookup latency and RAM access latency. On > the other hand, if the cache access mode is sequential ("sequential_access" > parameter set to "True"), tags and RAM are accessed sequentially. Therefore, > the hit latency is the sum of tag lookup latency plus RAM access latency. > > > Diffs > ----- > > configs/common/Caches.py UNKNOWN > src/mem/cache/BaseCache.py UNKNOWN > src/mem/cache/base.hh UNKNOWN > src/mem/cache/base.cc UNKNOWN > src/mem/cache/tags/Tags.py UNKNOWN > src/mem/cache/tags/base.hh UNKNOWN > src/mem/cache/tags/base.cc UNKNOWN > src/mem/cache/tags/base_set_assoc.hh UNKNOWN > src/mem/cache/tags/fa_lru.hh UNKNOWN > src/mem/cache/tags/fa_lru.cc UNKNOWN > > Diff: http://reviews.gem5.org/r/3502/diff/ > > > Testing > ------- > > Tested using --Debug-flags=Cache > > > Thanks, > > Sophiane SENNI > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
