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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3502/
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(Updated June 16, 2016, 6:55 p.m.)
Review request for Default.
Repository: gem5
Description (updated)
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Changeset 11536:1a3a96d435ed
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cache: Split the hit latency into tag lookup latency and RAM access latency
If the cache access mode is parallel ("sequential_access" parameter set to
"False"), tags and RAMs are accessed in parallel. Therefore, the hit latency is
the maximum latency between tag lookup latency and RAM access latency. On the
other hand, if the cache access mode is sequential ("sequential_access"
parameter set to "True"), tags and RAM are accessed sequentially. Therefore,
the hit latency is the sum of tag lookup latency plus RAM access latency.
Diffs (updated)
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src/mem/cache/tags/fa_lru.hh 80e79ae636ca
src/mem/cache/tags/base.cc 80e79ae636ca
src/mem/cache/tags/Tags.py 80e79ae636ca
src/mem/cache/tags/fa_lru.cc 80e79ae636ca
src/mem/cache/tags/base_set_assoc.hh 80e79ae636ca
src/mem/cache/tags/base.hh 80e79ae636ca
configs/common/Caches.py 80e79ae636ca
src/mem/cache/Cache.py 80e79ae636ca
src/mem/cache/base.hh 80e79ae636ca
src/mem/cache/base.cc 80e79ae636ca
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
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Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
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